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Commit 11fc2f68 authored by Vikram S. Adve's avatar Vikram S. Adve
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(1) Added special register class containing (for now) %fsr. 

    Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

llvm-svn: 6343
parent 6bbfe341
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