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Commit 1b1e25b7 authored by Daniel Sanders's avatar Daniel Sanders
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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal... 

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

llvm-svn: 191498
parent db4c21f9
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