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Commit 2ad0b373 authored by Andrew Trick's avatar Andrew Trick
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Added a check in the preRA scheduler for potential interference on a

induction variable. The preRA scheduler is unaware of induction vars,
so we look for potential "virtual register cycles" instead.

Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing

llvm-svn: 129100
parent d6f1c589
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