More DCE.

llvm-svn: 77231

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

@@ -163,12 +163,8 @@ namespace ARMII {
   ///
   enum Op {
     ADDri,
-    ADDrs,
-    ADDrr,
     MOVr,
-    SUBri,
-    SUBrs,
-    SUBrr
+    SUBri
   };
 }
 

llvm/lib/Target/ARM/ARMInstrInfo.cpp

@@ -66,12 +66,8 @@ unsigned ARMInstrInfo::
 getOpcode(ARMII::Op Op) const {
   switch (Op) {
   case ARMII::ADDri: return ARM::ADDri;
-  case ARMII::ADDrs: return ARM::ADDrs;
-  case ARMII::ADDrr: return ARM::ADDrr;
   case ARMII::MOVr: return ARM::MOVr;
   case ARMII::SUBri: return ARM::SUBri;
-  case ARMII::SUBrs: return ARM::SUBrs;
-  case ARMII::SUBrr: return ARM::SUBrr;
   default:
     break;
   }

llvm/lib/Target/ARM/Thumb1InstrInfo.cpp

@@ -33,12 +33,8 @@ unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
 unsigned Thumb1InstrInfo::getOpcode(ARMII::Op Op) const {
   switch (Op) {
   case ARMII::ADDri: return ARM::tADDi8;
-  case ARMII::ADDrs: return 0;
-  case ARMII::ADDrr: return ARM::tADDrr;
   case ARMII::MOVr: return ARM::tMOVr;
   case ARMII::SUBri: return ARM::tSUBi8;
-  case ARMII::SUBrs: return 0;
-  case ARMII::SUBrr: return ARM::tSUBrr;
   default:
     break;
   }

llvm/lib/Target/ARM/Thumb2InstrInfo.cpp

@@ -34,12 +34,8 @@ unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
 unsigned Thumb2InstrInfo::getOpcode(ARMII::Op Op) const {
   switch (Op) {
   case ARMII::ADDri: return ARM::t2ADDri;
-  case ARMII::ADDrs: return ARM::t2ADDrs;
-  case ARMII::ADDrr: return ARM::t2ADDrr;
   case ARMII::MOVr: return ARM::t2MOVr;
   case ARMII::SUBri: return ARM::t2SUBri;
-  case ARMII::SUBrs: return ARM::t2SUBrs;
-  case ARMII::SUBrr: return ARM::t2SUBrr;
   default:
     break;
   }