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Commit 3e7f88c1 authored by Juergen Ributzka's avatar Juergen Ributzka
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[MachineCombiner][AArch64] Use the correct register class for MADD, SUB, and OR. 

Select the correct register class for the various instructions that are
generated when combining instructions and constrain the registers to the
appropriate register class.

This fixes rdar://problem/18183707.

llvm-svn: 216805
parent c5c1c609
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