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This is an archived project. Repository and other project resources are read-only.
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Roger Ferrer
llvm-epi-0.8
Commits
43450cb0
Commit
43450cb0
authored
21 years ago
by
Chris Lattner
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Change all #include'd files to be :: rules instead of : rules
llvm-svn: 8019
parent
48210094
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2 changed files
llvm/lib/Target/Sparc/Makefile
+1
-1
1 addition, 1 deletion
llvm/lib/Target/Sparc/Makefile
llvm/lib/Target/X86/Makefile
+6
-6
6 additions, 6 deletions
llvm/lib/Target/X86/Makefile
with
7 additions
and
7 deletions
llvm/lib/Target/Sparc/Makefile
+
1
−
1
View file @
43450cb0
...
@@ -48,7 +48,7 @@ TARGET_NAME := SparcV9
...
@@ -48,7 +48,7 @@ TARGET_NAME := SparcV9
TABLEGEN_FILES
:=
$(
wildcard
*
.td
)
TABLEGEN_FILES
:=
$(
wildcard
*
.td
)
$(TARGET_NAME)CodeEmitter.inc
:
$(TABLEGEN_FILES) $(TBLGEN)
$(TARGET_NAME)CodeEmitter.inc
:
:
$(TABLEGEN_FILES) $(TBLGEN)
$(
TBLGEN
)
$(
TARGET_NAME
)
.td
-gen-emitter
-o
$@
$(
TBLGEN
)
$(
TARGET_NAME
)
.td
-gen-emitter
-o
$@
clean
::
clean
::
...
...
This diff is collapsed.
Click to expand it.
llvm/lib/Target/X86/Makefile
+
6
−
6
View file @
43450cb0
...
@@ -7,22 +7,22 @@ $(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
...
@@ -7,22 +7,22 @@ $(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
X86GenRegisterInfo.inc X86GenInstrNames.inc
\
X86GenRegisterInfo.inc X86GenInstrNames.inc
\
X86GenInstrInfo.inc X86GenInstrSelector.inc
X86GenInstrInfo.inc X86GenInstrSelector.inc
X86GenRegisterNames.inc
:
X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
X86GenRegisterNames.inc
:
:
X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
$(
TBLGEN
)
$<
-gen-register-enums
-o
$@
$(
TBLGEN
)
$<
-gen-register-enums
-o
$@
X86GenRegisterInfo.h.inc
:
X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
X86GenRegisterInfo.h.inc
:
:
X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
$(
TBLGEN
)
$<
-gen-register-desc-header
-o
$@
$(
TBLGEN
)
$<
-gen-register-desc-header
-o
$@
X86GenRegisterInfo.inc
:
X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
X86GenRegisterInfo.inc
:
:
X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
$(
TBLGEN
)
$<
-gen-register-desc
-o
$@
$(
TBLGEN
)
$<
-gen-register-desc
-o
$@
X86GenInstrNames.inc
:
X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
X86GenInstrNames.inc
:
:
X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
$(
TBLGEN
)
$<
-gen-instr-enums
-o
$@
$(
TBLGEN
)
$<
-gen-instr-enums
-o
$@
X86GenInstrInfo.inc
:
X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
X86GenInstrInfo.inc
:
:
X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
$(
TBLGEN
)
$<
-gen-instr-desc
-o
$@
$(
TBLGEN
)
$<
-gen-instr-desc
-o
$@
X86GenInstrSelector.inc
:
X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
X86GenInstrSelector.inc
:
:
X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
$(
TBLGEN
)
$<
-gen-instr-selector
-o
$@
$(
TBLGEN
)
$<
-gen-instr-selector
-o
$@
clean
::
clean
::
...
...
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