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Commit 54a2c326 authored by Richard Osborne's avatar Richard Osborne
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Handle MVT::i64 type in DAG combine for ISD::ADD. Fold 64 bit 

expression add(add(mul(x,y),a),b) -> lmul(x,y,a,b) if all
operands are zero extended.

llvm-svn: 98168
parent 7e3283c0
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