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Commit 561fcc0d authored by David Greene's avatar David Greene
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[X86-64] Fix 256-bit SET0 lowering for non-VLX targets 

If we don't have VLX then 256-bit SET0 should be lowered
to VPXOR with ZMM registers.  This restores functionality
accidentally removed by r309926.

Differential Revision: https://reviews.llvm.org/D62415

llvm-svn: 361843
parent ebe22a17
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