[CodeGen] allow printing of zero latency in sched comments

I don't know how to expose this in a test. There are ARM / AArch64 
sched classes that include zero latency instructions, but I'm not 
seeing sched info printed for those targets. X86 will almost 
certainly have these soon (see PR36671), but no model has
'let Latency = 0' currently.

llvm-svn: 327518