[tablegen] Improve performance on *GenRegisterInfo.inc by replacing...

[tablegen] Improve performance on *GenRegisterInfo.inc by replacing SparseVector with BitVector. NFC

Summary: Generating X86GenRegisterInfo.inc and AArch64GenRegisterInfo.inc is 8-9% faster on my build.

Reviewers: bogner, javed.absar

Reviewed By: bogner

Subscribers: llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D47907

llvm-svn: 334337