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Commit 7da7b974 authored by Craig Topper's avatar Craig Topper
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[X86] When iselling (x << C1) and/or/xor C2 as (x and/or/xor (C2>>C1)) << C1,...

[X86] When iselling (x << C1) and/or/xor C2 as (x and/or/xor (C2>>C1)) << C1, go through the isel table instead of manually selecting.

Previously we manually selected the AND/OR/XOR with immediate and the SHL(or ADD if the shift is 1). But this was missing out on the opportunity to use a 64 bit AND with a 32-bit immediate and possibly other isel tricks we have built into the tables.

Instead, insert the new nodes into the DAG using insertDAGNode and allow them each to be selected through the normal table.

llvm-svn: 357049
parent e204d244
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