"git@repo.hca.bsc.es:rferrer/llvm-epi-0.8.git" did not exist on "c8c38dbb187746d1cb40fd274bca467c7ba93cb3"
TableGen: Allow use of #NAME# outside of 'def' names.
Previously, def NAME values were only populated, and references to NAME resolved, when NAME was referenced in the 'def' entry of the multiclass sub-entry. e.g., multiclass foo<...> { def prefix_#NAME : ... } It's useful, however, to be able to reference NAME even when the default def name is used. For example, when a multiclass has 'def : Pat<...>' or 'def : InstAlias<...>' entries which refer to earlier instruction definitions in the same multiclass. e.g., multiclass myMulti<RegisterClass rc> { def _r : myI<(outs rc:$d), (ins rc:$r), "r $d, $r", []>; def : InstAlias<\"wilma $r\", (!cast<Instruction>(NAME#\"_r\") rc:$r, rc:$r)>; } llvm-svn: 161198
Loading
Please register or sign in to comment