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Commit bfd3ea32 authored by Oliver Stannard's avatar Oliver Stannard
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[ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP

The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and
FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be
modeled using the same target feature, and all double-precision
operations are already disabled by the fp-only-sp target features.

llvm-svn: 218748
parent 37e4daab
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