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Commit c58ef7de authored by Evan Cheng's avatar Evan Cheng
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Add support for _mm_cmp{cc}_ss and _mm_cmp{cc}_ps intrinsics 

llvm-svn: 27256
parent 59331001
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llvm/include/llvm/IntrinsicsX86.td
+ 4
− 106
View file @ c58ef7de
...@@ -63,114 +63,12 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". ...@@ -63,114 +63,12 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
// Comparison ops // Comparison ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse_cmpeq_ss : GCCBuiltin<"__builtin_ia32_cmpeqss">, def int_x86_sse_cmp_ss :
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>; llvm_v4f32_ty, llvm_sbyte_ty], [InstrNoMem]>;
def int_x86_sse_cmpeq_ps : GCCBuiltin<"__builtin_ia32_cmpeqps">, def int_x86_sse_cmp_ps :
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmplt_ss : GCCBuiltin<"__builtin_ia32_cmpltss">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmplt_ps : GCCBuiltin<"__builtin_ia32_cmpltps">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmple_ss : GCCBuiltin<"__builtin_ia32_cmpless">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmple_ps : GCCBuiltin<"__builtin_ia32_cmpleps">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmpgt_ss : GCCBuiltin<"__builtin_ia32_cmpgtss">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmpgt_ps : GCCBuiltin<"__builtin_ia32_cmpgtps">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmpge_ss : GCCBuiltin<"__builtin_ia32_cmpgess">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmpge_ps : GCCBuiltin<"__builtin_ia32_cmpgeps">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmpneq_ss : GCCBuiltin<"__builtin_ia32_cmpneqss">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmpneq_ps : GCCBuiltin<"__builtin_ia32_cmpneqps">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmpnlt_ss : GCCBuiltin<"__builtin_ia32_cmpnltss">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmpnlt_ps : GCCBuiltin<"__builtin_ia32_cmpnltps">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmpnle_ss : GCCBuiltin<"__builtin_ia32_cmpnless">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmpnle_ps : GCCBuiltin<"__builtin_ia32_cmpnleps">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty, Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>; llvm_v4f32_ty, llvm_sbyte_ty], [InstrNoMem]>;
def int_x86_sse_cmpngt_ss : GCCBuiltin<"__builtin_ia32_cmpngtss">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmpngt_ps : GCCBuiltin<"__builtin_ia32_cmpngtps">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmpnge_ss : GCCBuiltin<"__builtin_ia32_cmpngess">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmpnge_ps : GCCBuiltin<"__builtin_ia32_cmpngeps">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmpord_ss : GCCBuiltin<"__builtin_ia32_cmpordss">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmpord_ps : GCCBuiltin<"__builtin_ia32_cmpordps">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmpunord_ss : GCCBuiltin<"__builtin_ia32_cmpunordss">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_cmpunord_ps : GCCBuiltin<"__builtin_ia32_cmpunordps">,
Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_comieq_ss : GCCBuiltin<"__builtin_ia32_comieq">,
Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_comilt_ss : GCCBuiltin<"__builtin_ia32_comilt">,
Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_comile_ss : GCCBuiltin<"__Builtin_ia32_comile">,
Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_comigt_ss : GCCBuiltin<"__builtin_ia32_comigt">,
Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_comige_ss : GCCBuiltin<"__builtin_ia32_comige">,
Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_comineq_ss : GCCBuiltin<"__builtin_ia32_comineq">,
Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_ucomieq_ss : GCCBuiltin<"__builtin_ia32_ucomieq">,
Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_ucomilt_ss : GCCBuiltin<"__builtin_ia32_ucomilt">,
Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_ucomile_ss : GCCBuiltin<"__Builtin_ia32_ucomile">,
Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_ucomigt_ss : GCCBuiltin<"__builtin_ia32_ucomigt">,
Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_ucomige_ss : GCCBuiltin<"__builtin_ia32_ucomige">,
Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
def int_x86_sse_ucomineq_ss : GCCBuiltin<"__builtin_ia32_ucomineq">,
Intrinsic<[llvm_int_ty, llvm_v4f32_ty,
llvm_v4f32_ty], [InstrNoMem]>;
} }
......
llvm/lib/Target/X86/X86InstrSSE.td
+ 35
− 9
View file @ c58ef7de
...@@ -501,7 +501,8 @@ def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src), ...@@ -501,7 +501,8 @@ def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
let isTwoAddress = 1 in { let isTwoAddress = 1 in {
def CMPSSrr : SSI<0xC2, MRMSrcReg, def CMPSSrr : SSI<0xC2, MRMSrcReg,
(ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc), (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
"cmp${cc}ss {$src, $dst|$dst, $src}", []>; "cmp${cc}ss {$src, $dst|$dst, $src}",
[]>;
def CMPSSrm : SSI<0xC2, MRMSrcMem, def CMPSSrm : SSI<0xC2, MRMSrcMem,
(ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc), (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
"cmp${cc}ss {$src, $dst|$dst, $src}", []>; "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
...@@ -526,6 +527,27 @@ def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2), ...@@ -526,6 +527,27 @@ def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
"ucomisd {$src2, $src1|$src1, $src2}", "ucomisd {$src2, $src1|$src1, $src2}",
[(X86cmp FR64:$src1, (loadf64 addr:$src2))]>; [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
// Aliases to match intrinsics which expect XMM operand(s).
let isTwoAddress = 1 in {
def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
"cmp${cc}ss {$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
VR128:$src, imm:$cc))]>;
def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
"cmp${cc}ss {$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
(load addr:$src), imm:$cc))]>;
def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
"cmp${cc}sd {$src, $dst|$dst, $src}", []>;
def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
"cmp${cc}sd {$src, $dst|$dst, $src}", []>;
}
// Aliases of packed instructions for scalar use. These all have names that // Aliases of packed instructions for scalar use. These all have names that
// start with 'Fs'. // start with 'Fs'.
...@@ -936,17 +958,21 @@ def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2), ...@@ -936,17 +958,21 @@ def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
let isTwoAddress = 1 in { let isTwoAddress = 1 in {
def CMPPSrr : PSI<0xC2, MRMSrcReg, def CMPPSrr : PSI<0xC2, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc), (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
"cmp${cc}ps {$src, $dst|$dst, $src}", []>; "cmp${cc}ps {$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
VR128:$src, imm:$cc))]>;
def CMPPSrm : PSI<0xC2, MRMSrcMem, def CMPPSrm : PSI<0xC2, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc), (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
"cmp${cc}ps {$src, $dst|$dst, $src}", []>; "cmp${cc}ps {$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
(load addr:$src), imm:$cc))]>;
def CMPPDrr : PDI<0xC2, MRMSrcReg, def CMPPDrr : PDI<0xC2, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc), (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
"cmp${cc}pd {$src, $dst|$dst, $src}", []>; "cmp${cc}pd {$src, $dst|$dst, $src}", []>;
def CMPPDrm : PDI<0xC2, MRMSrcMem, def CMPPDrm : PDI<0xC2, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc), (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
"cmp${cc}pd {$src, $dst|$dst, $src}", []>; "cmp${cc}pd {$src, $dst|$dst, $src}", []>;
} }
// Shuffle and unpack instructions // Shuffle and unpack instructions
......
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