Skip to content
Commit d31802c1 authored by Evan Cheng's avatar Evan Cheng
Browse files

Add x86 isel lowering logic to form bit test with inverted condition. e.g. 

x ^ -1.

Patch by David Majnemer.
rdar://12755626

llvm-svn: 169339
parent 8edae13d
Hide whitespace changes
Inline Side-by-side
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment