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Commit fce28914 authored by Chad Rosier's avatar Chad Rosier
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Tidy up. 

llvm-svn: 146568
parent a342667f
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llvm/lib/Target/ARM/ARMFastISel.cpp
+ 2
− 1
View file @ fce28914
...@@ -1130,7 +1130,6 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr, ...@@ -1130,7 +1130,6 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
break; break;
case MVT::f32: case MVT::f32:
if (!Subtarget->hasVFP2()) return false; if (!Subtarget->hasVFP2()) return false;
StrOpc = ARM::VSTRS;
// Unaligned stores need special handling. Floats require word-alignment. // Unaligned stores need special handling. Floats require word-alignment.
if (Alignment && Alignment < 4) { if (Alignment && Alignment < 4) {
unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32)); unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
...@@ -1140,6 +1139,8 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr, ...@@ -1140,6 +1139,8 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
SrcReg = MoveReg; SrcReg = MoveReg;
VT = MVT::i32; VT = MVT::i32;
StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12; StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
} else {
StrOpc = ARM::VSTRS;
} }
break; break;
case MVT::f64: case MVT::f64:
......
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