llvm-svn: 107560

llvm-svn: 107558

llvm-svn: 107552

Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.

llvm-svn: 107550

llvm-svn: 107549

llvm-svn: 107540

- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode

llvm-svn: 107523

llvm-svn: 107513

- X86 unfolding should check if the instructions being unfolded has memoperands.
  If there is no memoperands, then it must assume conservative alignment. If this
  would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand
  etc. should not unfold the instruction.

llvm-svn: 107509

llvm-svn: 107500

llvm-svn: 107498

that it checks the immediate values, not just the instructions opcodes.
Radar 8110263.

llvm-svn: 107487

llvm-svn: 107482

llvm-svn: 107448

llvm-svn: 107438

getFunctionAlignment and the corresponding use of that value in the ARM
asm printer, but now we're using the standard asm printer.  The result of
this was that function alignments were dropped completely for Thumb functions.
Radar 8143571.

llvm-svn: 107435

Objective-C metadata types which should be marked as "weak", but which the
linker will remove upon final linkage. However, this linkage isn't specific to
Objective-C.

For example, the "objc_msgSend_fixup_alloc" symbol is defined like this:

      .globl l_objc_msgSend_fixup_alloc
      .weak_definition l_objc_msgSend_fixup_alloc
      .section __DATA, __objc_msgrefs, coalesced
      .align 3
l_objc_msgSend_fixup_alloc:
       .quad   _objc_msgSend_fixup
       .quad   L_OBJC_METH_VAR_NAME_1

This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".

Currently only supported on Darwin platforms.

llvm-svn: 107433

Add AVX SSE3 packed horizontal and & sub instructions

llvm-svn: 107405

llvm-svn: 107404

llvm-svn: 107377

to SelectionDAG.

llvm-svn: 107376

llvm-svn: 107375

the same address.

llvm-svn: 107373

- Add AVX SSE2 Move doubleword and quadword instructions.
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.

llvm-svn: 107365

llvm-svn: 107308

llvm-svn: 107306

llvm-svn: 107300

llvm-svn: 107293

llvm-svn: 107280

llvm-svn: 107246

llvm-svn: 107245

llvm-svn: 107243

llvm-svn: 107241

llvm-svn: 107240

- Add VEX encoding bits to x86 MRM0r-MRM7r

llvm-svn: 107238

llvm-svn: 107225

llvm-svn: 107215

llvm-svn: 107213

llvm-svn: 107211

llvm-svn: 107206