llvm-svn: 63808

llvm-svn: 63800

Adjust callers.

llvm-svn: 63789

and llvm-gcc.

llvm-svn: 63786

Adjust the many callers of those versions.

llvm-svn: 63767

target directories themselves.  This also means that VMCore no longer
needs to know about every target's list of intrinsics.  Future work
will include converting the PowerPC target to this interface as an
example implementation.

llvm-svn: 63765

llvm-svn: 63752

SSE disabled.

llvm-svn: 63751

llvm-svn: 63740

of Lod and Sto; patch uses.

llvm-svn: 63716

functions, with callers adjusted to fit.

llvm-svn: 63705

functions.

llvm-svn: 63703

of undefs and incorrectly determining if we have punpckldq.

llvm-svn: 63702

llvm-svn: 63693

llvm-svn: 63674

have it yet.  More coming.

llvm-svn: 63673

llvm-svn: 63664

llvm-svn: 63656

llvm-svn: 63650

is given, override the subtarget settings and enable 64-bit support.
This restores the earlier behavior, and fixes regressions on
Non-64-bit-capable x86-32 hosts.

This isn't necessarily the best approach, but the most obvious
alternative is to require -mcpu=x86-64 or -mattr=+64bit to be used
with -march=x86-64 when the host doesn't have 64-bit support. This
makes things little more consistent, but it's less convenient, and
it has the practical drawback of requiring lots of test changes, so
I opted for the above approach for now.

llvm-svn: 63642

created. Specifically, those BuildMIs which use
"DebugLoc::getUnknownLoc()". I'll remove them soon.

llvm-svn: 63584

SSE2, however it's possible to disable SSE2, and the subtarget support
code thinks that if 64-bit implies SSE2 and SSE2 is disabled then
64-bit should also be disabled. Instead, just mark all the 64-bit
subtargets as explicitly supporting SSE2.

Also, move the code that makes -march=x86-64 enable 64-bit support by
default to only apply when there is no explicit subtarget. If you
need to specify a subtarget and you want 64-bit code, you'll need to
select a subtarget that supports 64-bit code.

llvm-svn: 63575

Add an assert to check HasX86_64 status.

llvm-svn: 63552

llvm-svn: 63542

Made the common case of default address space directive as non-virtual for performance reasons. Provide a single virtual interface for directives of all sizes in  non-default address spaces.

llvm-svn: 63521

llvm-svn: 63509

llvm-svn: 63506

Teach LowerBRCOND to recognize (xor (setcc x), 1). The xor inverts the condition. It's normally transformed by the dag combiner, unless the condition is set by a arithmetic op with overflow.

llvm-svn: 63505

var-args, and don't allow FP return values

llvm-svn: 63495

crashes or wrong code with codegen of large integers:
eliminate the legacy getIntegerVTBitMask and
getIntegerVTSignBit methods, which returned their
value as a uint64_t, so couldn't handle huge types.

llvm-svn: 63494

argument.  Adjust all callers and overloaded versions.

llvm-svn: 63444

llvm-svn: 63442

llvm-svn: 63387

llvm-svn: 63382

an illegal type.

llvm-svn: 63380

Enable emitting of constant values in non-default address space as well. The APIs emitting constants now take an additional parameter signifying the address space in which to emit. The APIs like getData8BitsDirective() etc are made virtual enabling targets to be able to define appropirate directivers for various sizes and address spaces.

llvm-svn: 63377

dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.

llvm-svn: 63266

llvm-svn: 63252

llvm-svn: 63198

The memory alignment requirement on some of the mov{h|l}p{d|s} patterns are 16-byte. That is overly strict. These instructions read / write f64 memory locations without alignment requirement.

llvm-svn: 63195