Add RCBarriers to TargetInstrDesc. It's a list of register classes the given instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers.

TableGen has been taught to generate the lists from instruction definitions.

llvm-svn: 57722

constants that don't fit in an int. This fixes
"this decimal constant is unsigned only in ISO C90"
warnings.

llvm-svn: 57668

use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.

A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.

To support this, teach tablegen how to handle 64-bit constants.

llvm-svn: 57663

This will allow predicates to be composed, which will allow the
predicate definitions to become less redundant, and eventually
will allow DAGISelEmitter.cpp to emit less redundant code.

llvm-svn: 57562

Patch by Samuel Tardieu.

llvm-svn: 57291

in tblgen.  This is PR2827, thanks to Waldemar Knorr for tracking this
down.

llvm-svn: 57124

llvm-svn: 56963

they'll be a little more visible. Also, update and reword them a bit.

llvm-svn: 56877

helper functions instead of duplicating it inline each time
it is needed. This eliminates a few hundred or so copies
of this code in each target.

llvm-svn: 56759

consistancy with ConstantInt, and re-implement it in terms
of ConstantInt's getSExtValue.

llvm-svn: 56700

s/ParamAttr/Attribute/g
s/PAList/AttrList/g
s/FnAttributeWithIndex/AttributeWithIndex/g
s/FnAttr/Attribute/g

This sets the stage 
- to implement function notes as function attributes and 
- to distinguish between function attributes and return value attributes.

This requires corresponding changes in llvm-gcc and clang.

llvm-svn: 56622

llvm-svn: 56466

llvm-svn: 56465

llvm-svn: 56463

llvm-svn: 56462

llvm-svn: 56459

llvm-svn: 56458

llvm-svn: 56419

llvm-svn: 56275

Apologies for the thrashing.

llvm-svn: 56251

- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol

These changes pave the way to allowing SymbolSDNodes with non-external linkage.

llvm-svn: 56249

ConstantFP* instead of APInt and APFloat directly.

This reduces the amount of time to create ConstantSDNode
and ConstantFPSDNode nodes when ConstantInt* and ConstantFP*
respectively are already available, as is the case in
SelectionDAGBuild.cpp. Also, it reduces the amount of time
to legalize constants into constant pools, and the amount of
time to add ConstantFP operands to MachineInstrs, due to
eliminating ConstantInt::get and ConstantFP::get calls.

It increases the amount of work needed to create new constants
in cases where the client doesn't already have a ConstantInt*
or ConstantFP*, such as legalize expanding 64-bit integer constants
to 32-bit constants. And it adds a layer of indirection for the
accessor methods. But these appear to be outweight by the benefits
in most cases.

It will also make it easier to make ConstantSDNode and
ConstantFPNode more consistent with ConstantInt and ConstantFP.

llvm-svn: 56162

with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159

llvm-svn: 56107

by its first field, but TableGen doesn't actually enforce creating it that 
way. TableGen sorts the records that will be used to create it by the names 
of the records, not the Name field of those records.

This patch corrects the sort to use the "Name" field of the record as the 
sort key.

llvm-svn: 56106

Change getSubReg semantics. It now returns zero if the specified register doesn't have a subreg of the specified index.

llvm-svn: 56099

llvm-svn: 55916

Correctly handle physical register inputs. They are not explicit input operands in the resulting machine instrs.

llvm-svn: 55893

llvm-svn: 55878

llvm-svn: 55876

def : Pat<(i8 (trunc GR32:$src)),
          (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>

llvm-svn: 55875

Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class.

llvm-svn: 55679

Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes.

llvm-svn: 55623

llvm-svn: 55545

llvm-svn: 55512

llvm-svn: 55504

Add support for fast-isel of opcodes that require use of extract_subreg.  Because of how extract_subreg is treated, it requires special case handling.

llvm-svn: 55480

llvm-svn: 55418

llvm-svn: 55401

llvm-svn: 55394