llvm-svn: 27555

llvm-svn: 27554

llvm-svn: 27544

llvm-svn: 27543

letting the code generator handle them directly.

llvm-svn: 27539

constant pool load.

llvm-svn: 27538

No functionality changes.

llvm-svn: 27536

them.

llvm-svn: 27534

llvm-svn: 27506

llvm-svn: 27501

llvm-svn: 27497

llvm-svn: 27496

entry point of a function.

llvm-svn: 27494

llvm-svn: 27491

Also MOVPDI2DIrr.

llvm-svn: 27476

- Normalize shuffle nodes so result vector lower half elements come from the
  first vector, the rest come from the second vector. (Except for the
  exceptions :-).
- Other minor fixes.

llvm-svn: 27474

llvm-svn: 27473

llvm-svn: 27471

llvm-svn: 27470

llvm-svn: 27469

Convert vsldoi(x,x) to work the same way other (x,x) cases work.

llvm-svn: 27467

llvm-svn: 27463

llvm-svn: 27460

llvm-svn: 27457

llvm-svn: 27453

lower it and LLVM to have one fewer intrinsic.  This implements
CodeGen/PowerPC/vec_shuffle.ll

llvm-svn: 27450

vperm with a perm mask lvx'd from the constant pool.

llvm-svn: 27448

llvm-svn: 27446

llvm-svn: 27445

llvm-svn: 27444

llvm-svn: 27442

llvm-svn: 27440

llvm-svn: 27439

vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>

This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.

It would match a {p}unpckl on x86.

llvm-svn: 27437

llvm-svn: 27434

llvm-svn: 27433

llvm-svn: 27427

llvm-svn: 27425

llvm-svn: 27423

llvm-svn: 27421