- Jul 29, 2011
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Nick Lewycky authored
lines. No functionality change. llvm-svn: 136458
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Eli Friedman authored
working on x86 (at least for trivial testcases); other architectures will need more work so that they actually emit the appropriate instructions for orderings stricter than 'monotonic'. (As far as I can tell, the ARM, PPC, Mips, and Alpha backends need such changes.) llvm-svn: 136457
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Jakub Staszak authored
rounding errors. llvm-svn: 136456
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Chandler Carruth authored
First off, only depend on the actual MC-ized disassemblers in the targets, not all of the libraries those in turn depend on. Second off, only depend on those MC-ized disassemblers for targets we're building. This should fix builds of fewer than all targets. llvm-svn: 136455
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Bruno Cardoso Lopes authored
on the second half must be reindexed. llvm-svn: 136454
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Bruno Cardoso Lopes authored
generation to always catch the weird cases. llvm-svn: 136453
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Bruno Cardoso Lopes authored
llvm-svn: 136452
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Bruno Cardoso Lopes authored
llvm-svn: 136451
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Bruno Cardoso Lopes authored
undef mask elements. This fixes PR10529. llvm-svn: 136450
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Bruno Cardoso Lopes authored
Also tidy up code a bit. llvm-svn: 136449
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Bruno Cardoso Lopes authored
Also make PALIGNR masks to don't match 256-bits, which isn't supported It's also a step to solve PR10489 llvm-svn: 136448
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Bill Wendling authored
With this, we can now compile a simple EH program. llvm-svn: 136446
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Bill Wendling authored
llvm-svn: 136445
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Bill Wendling authored
llvm-svn: 136444
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Jakob Stoklund Olesen authored
Later passes /are/ using this information when running the register scavenger. This fixes the second problem in PR10520. llvm-svn: 136440
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Jakob Stoklund Olesen authored
This hidden llc option runs the machine code verifier after expanding ARM pseudo-instructions, but before if-conversion. The machine code verifier is much better at pointing out liveness errors that can trip up the register scavenger. llvm-svn: 136439
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Eli Friedman authored
Make sure to correctly clear the exact/nuw/nsw flags off of shifts when they are combined together. <rdar://problem/9859829> llvm-svn: 136435
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Chandler Carruth authored
specified in the same file that the library itself is created. This is more idiomatic for CMake builds, and also allows us to correctly specify dependencies that are missed due to bugs in the GenLibDeps perl script, or change from compiler to compiler. On Linux, this returns CMake to a place where it can relably rebuild several targets of LLVM. I have tried not to change the dependencies from the ones in the current auto-generated file. The only places I've really diverged are in places where I was seeing link failures, and added a dependency. The goal of this patch is not to start changing the dependencies, merely to move them into the correct location, and an explicit form that we can control and change when necessary. This also removes a serialization point in the build because we don't have to scan all the libraries before we begin building various tools. We no longer have a step of the build that regenerates a file inside the source tree. A few other associated cleanups fall out of this. This isn't really finished yet though. After talking to dgregor he urged switching to a single CMake macro to construct libraries with both sources and dependencies in the arguments. Migrating from the two macros to that style will be a follow-up patch. Also, llvm-config is still generated with GenLibDeps.pl, which means it still has slightly buggy dependencies. The internal CMake 'llvm-config-like' macro uses the correct explicitly specified dependencies however. A future patch will switch llvm-config generation (when using CMake) to be based on these deps as well. This may well break Windows. I'm getting a machine set up now to dig into any failures there. If anyone can chime in with problems they see or ideas of how to solve them for Windows, much appreciated. llvm-svn: 136433
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Jakub Staszak authored
llvm-svn: 136432
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Owen Anderson authored
llvm-svn: 136431
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Bill Wendling authored
This generates the correct SDNodes for the landingpad instruction. It makes an assumption that the result of the landingpad instruction has at least two values. And that the first value is a pointer to the exception object and the second value is the "selector." llvm-svn: 136430
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Bill Wendling authored
AddLandingPadInfo takes a landingpad instruction and grabs all of the information from it that it needs for EH table generation. llvm-svn: 136429
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Jakub Staszak authored
LBH_TAKEN_WEIGHT + LBH_NONTAKEN_WEIGHT = 128 which in _most_ cases reduce number of rounding errors. llvm-svn: 136428
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Jim Grosbach authored
llvm-svn: 136427
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- Jul 28, 2011
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Jim Grosbach authored
llvm-svn: 136408
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Jim Grosbach authored
Add parsing support for BLX (immediate). Since the register operand version is predicated and the label operand version is not, we have to use some special handling to get the operand list right for matching. llvm-svn: 136406
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Owen Anderson authored
llvm-svn: 136405
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Eli Friedman authored
'atomicrmw' instructions, which allow representing all the current atomic rmw intrinsics. The allowed operands for these instructions are heavily restricted at the moment; we can probably loosen it a bit, but supporting general first-class types (where it makes sense) might get a bit complicated, given how SelectionDAG works. As an initial cut, these operations do not support specifying an alignment, but it would be possible to add if we think it's useful. Specifying an alignment lower than the natural alignment would be essentially impossible to support on anything other than x86, but specifying a greater alignment would be possible. I can't think of any useful optimizations which would use that information, but maybe someone else has ideas. Optimizer/codegen support coming soon. llvm-svn: 136404
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Jakub Staszak authored
llvm-svn: 136403
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Jakub Staszak authored
llvm-svn: 136402
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Jakob Stoklund Olesen authored
Code like that would only be produced by bugpoint, but we should still handle it correctly. When a register is defined by a REG_SEQUENCE of undefs, the register itself is undef. Previously, we would create a register with uses but no defs. Fixes part of PR10520. llvm-svn: 136401
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Jim Grosbach authored
llvm-svn: 136400
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Jim Grosbach authored
Add parsing support that handles converting the lsb+width source into the odd way we represent the instruction (an inverted bitfield mask). llvm-svn: 136399
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Jakub Staszak authored
there is no frequency difference whether condition is in the header or in the latch. llvm-svn: 136398
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Bill Wendling authored
llvm-svn: 136396
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Bill Wendling authored
llvm-svn: 136392
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Douglas Gregor authored
llvm-svn: 136390
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Jakob Stoklund Olesen authored
There are two conflicting strategies in play: - Under high register pressure, we want to assign large live ranges first. Smaller live ranges are easier to place afterwards. - Live range splitting is guided by interference, so splitting should be deferred until interference is as realistic as possible. With the recent changes to the live range stages, and with compact regions enabled, it is less traumatic to split a live range too early. If some of the split products were too big, they can often be split again. By reversing the RS_Split order, we get this queue order: 1. Normal live ranges, large to small. 2. RS_Split live ranges, large to small. The large-to-small order improves RAGreedy's puzzle solving skills under high register pressure. It may cause a bit more iterated splitting, but we handle that better now. With this change, -compact-regions is mostly an improvement on SPEC. llvm-svn: 136388
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Bill Wendling authored
This should be the only code necessary for DWARF EH prepare. llvm-svn: 136387
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Jakub Staszak authored
llvm-svn: 136384
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