- May 20, 2013
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Justin Holewinski authored
This converter currently only handles global variables in address space 0. For these variables, they are promoted to address space 1 (global memory), and all uses are updated to point to the result of a cvta.global instruction on the new variable. The motivation for this is address space 0 global variables are illegal since we cannot declare variables in the generic address space. Instead, we place the variables in address space 1 and explicitly convert the pointer to address space 0. This is primarily intended to help new users who expect to be able to place global variables in the default address space. llvm-svn: 182254
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Justin Holewinski authored
[NVPTX] Fix i1 kernel parameters and global variables. ABI rules say we need to use .u8 for i1 parameters for kernels. llvm-svn: 182253
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Sergey Matveev authored
We need this to avoid races when ASan and LSan are used together. llvm-svn: 182252
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Sergey Matveev authored
llvm-svn: 182251
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Sergey Matveev authored
llvm-svn: 182250
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Sergey Matveev authored
Leak checking functionality which will be shared between LSan/ASan/MSan. llvm-svn: 182249
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Sergey Matveev authored
llvm-svn: 182248
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Sergey Matveev authored
llvm-svn: 182247
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Sergey Matveev authored
llvm-svn: 182246
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Sergey Matveev authored
This is the first in a series of CLs implementing LeakSanitizer. http://clang.llvm.org/docs/LeakSanitizer.html llvm-svn: 182245
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Timur Iskhodzhanov authored
Also fix wrong alignment maths and an outdated comment llvm-svn: 182238
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Stepan Dyatkovskiy authored
Introduction: In case when stack alignment is 8 and GPRs parameter part size is not N*8: we add padding to GPRs part, so part's last byte must be recovered at address K*8-1. We need to do it, since remained (stack) part of parameter starts from address K*8, and we need to "attach" "GPRs head" without gaps to it: Stack: |---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes... [ [padding] [GPRs head] ] [ ------ Tail passed via stack ------ ... FIX: Note, once we added padding we need to correct *all* Arg offsets that are going after padded one. That's why we need this fix: Arg offsets were never corrected before this patch. See new test-cases included in patch. We also don't need to insert padding for byval parameters that are stored in GPRs only. We need pad only last byval parameter and only in case it outsides GPRs and stack alignment = 8. Though, stack area, allocated for recovered byval params, must satisfy "Size mod 8 = 0" restriction. This patch reduces stack usage for some cases: We can reduce ArgRegsSaveArea since inner N*4 bytes sized byval params my be "packed" with alignment 4 in some cases. llvm-svn: 182237
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Renato Golin authored
llvm-svn: 182235
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Kostya Serebryany authored
[sanitizer] factor out ByteMap from SizeClassAllocator32 so that it can be later replaced with a more memory-efficient implementation on 64-bit. llvm-svn: 182234
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Bob Wilson authored
The export list for this test requires the following symbols to be available: JITTest_AvailableExternallyFunction JITTest_AvailableExternallyGlobal The change in r181200 commented them out, which caused the test to fail to link, at least on Darwin. I have only reverted the change for arm, since I can't test the other targets and since it sounds like that change was fixing real problems for those other targets. It should be possible to rearrange the code to keep those definitions outside the #ifdefs, but that should be done by someone who can reproduce the problems that r181200 was trying to fix. llvm-svn: 182233
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David Blaikie authored
Revert "Revert "Debug Info: Using declarations/DW_TAG_imported_declaration of variables, types, and functions."" This reverts commit r181947 (git d2990ce56a16050cac0d7937ec9919ff54c6df62 ) This addresses one of the two issues identified in r181947, ensuring that types imported via using declarations only result in a declaration being emitted for the type, not a definition. The second issue (emitting using declarations that are unused) is hopefully an acceptable increase as the real fix for this would be a bit difficult (probably at best we could record which using directives were involved in lookups - but may not have been the result of the lookup). This also ensures that DW_TAG_imported_declarations (& directives) are not emitted in line-tables-only mode as well as ensuring that typedefs only require/emit declarations (rather than definitions) for referenced types. llvm-svn: 182231
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Shankar Easwaran authored
so that their names are hidden. This addresses comments raised by Sean/Rafael. llvm-svn: 182230
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Jakob Stoklund Olesen authored
llvm-svn: 182229
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Jakob Stoklund Olesen authored
llvm-svn: 182228
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Jakob Stoklund Olesen authored
llvm-svn: 182227
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Benjamin Kramer authored
llvm-svn: 182226
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- May 19, 2013
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Jakob Stoklund Olesen authored
The wired physreg doesn't work on tied operands like on MOVXCC. Add a README note to fix this later. llvm-svn: 182225
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Jakob Stoklund Olesen authored
llvm-svn: 182224
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rdar://problem/13924072Bob Wilson authored
This fixes a bootstrapping problem with builds for Apple ARM targets. Clang had the wrong prototype for __clear_cache with ARM targets. Rafael fixed that in clang svn r181784 and r181810, but without those changes, we can't build this code for ARM because clang reports an error about the declaration in Memory.inc not matching the builtin declaration. Some of our buildbots need to use an older compiler that doesn't have the clang fix. Since __clear_cache is never used here when __APPLE__ is defined, I'm just conditionalizing the declaration to match that. I also moved the declaration of sys_icache_invalidate inside the conditional for __APPLE__ while I was at it. llvm-svn: 182223
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Jakob Stoklund Olesen authored
llvm-svn: 182222
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Jakob Stoklund Olesen authored
Also clean up the arguments to all the MOVCC instructions so the operands always are (true-val, false-val, cond-code). llvm-svn: 182221
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Renato Golin authored
llvm-svn: 182220
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Venkatraman Govindaraju authored
[Sparc] Rearrange integer registers' allocation order so that register allocator will use I and G registers before using L and O registers. Also, enable registers %g2-%g4 to be used in application and %g5 in 64 bit mode. llvm-svn: 182219
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Richard Smith authored
llvm-svn: 182218
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Tim Northover authored
llvm-svn: 182217
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Jakob Stoklund Olesen authored
llvm-svn: 182216
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Jakob Stoklund Olesen authored
Other operating systems, including FreeBSD and NetBSD, use long. llvm-svn: 182215
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Tim Northover authored
AArch64 ELF uses .rela relocations so there's no need to actually make use of the bits we're setting in the destination However, we should make sure all bits are cleared properly since multiple runs of resolveRelocations are possible and these could combine to produce invalid results if stale versions remain in the code. llvm-svn: 182214
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Tim Northover authored
lli's remote MCJIT code calls setExecutable just prior to running code. In line with Darwin behaviour this seems to be the place to invalidate any caches needed so that relocations can take effect properly. llvm-svn: 182213
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Bob Wilson authored
llvm-svn: 182212
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Benjamin Kramer authored
llvm-svn: 182211
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Tim Northover authored
On 32-bit hosts %p can print garbage when given a uint64_t, we should use %llx instead. This only affects the output of the debugging text produced by lli. llvm-svn: 182209
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Richard Smith authored
llvm-svn: 182207
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Alexander Kornienko authored
Summary: + improved handling of default style and predefined styles. Reviewers: djasper, klimek Reviewed By: klimek CC: cfe-commits Differential Revision: http://llvm-reviews.chandlerc.com/D813 llvm-svn: 182205
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Anna Zaks authored
llvm-svn: 182204
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