This is still a work in progress but most of the NEON instruction set
is supported.

llvm-svn: 73919

another change that makes the types ambiguous (at least as far as tablegen
is concerned).

llvm-svn: 73909

caller-saved register.

llvm-svn: 73901

Latency information for ARM v6. It's rough and not yet hooked up. Right now  we are only using branch latency to determine if-conversion limits.

llvm-svn: 73747

Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.

llvm-svn: 73622

llvm-svn: 73428

- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.

llvm-svn: 73381

llvm-svn: 73252

llvm-svn: 72593

llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add
a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html.
(llvm.eh.sjlj.longjmp documentation coming when that implementation is
added).

llvm-svn: 71758

a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but
rather used by the front-end as target hooks for exception handling.

llvm-svn: 71610

llvm-svn: 63852

llvm-svn: 60487

llvm-svn: 59314

llvm-svn: 59230

llvm-svn: 59107

llvm-svn: 58836

llvm-svn: 58828

llvm-svn: 58818

- Consolidate instruction formats.
- Other clean up.

llvm-svn: 58808

llvm-svn: 58800

llvm-svn: 58793

llvm-svn: 58790

llvm-svn: 58789

llvm-svn: 58780

Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.

llvm-svn: 58764

Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.

llvm-svn: 58626

llvm-svn: 58527

llvm-svn: 57524

parameters instead of raw Constants.  This prevents the constants from
being selected by the isel pass, fixing PR2735.

llvm-svn: 57385

Unconditional branch instruction encoding fix. Needs to use ABI, not AXI, to get the proper opcode bits.

llvm-svn: 57262

llvm-svn: 57251

llvm-svn: 56277

llvm-svn: 56180

llvm-svn: 56176

with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159

llvm-svn: 55601

llvm-svn: 55599

llvm-svn: 55598

llvm-svn: 55596