llvm-svn: 27588

llvm-svn: 27491

more than the OS keeps the stack aligned.

llvm-svn: 27381

llvm-svn: 27225

llvm-svn: 27180

llvm-svn: 26994

_foo2:
        extsw r2, r3
        std r2, -8(r1)
        lfd f0, -8(r1)
        fcfid f0, f0
        frsp f1, f0
        blr

instead of this:

_foo2:
        lis r2, ha16(LCPI2_0)
        lis r4, 17200
        xoris r3, r3, 32768
        stw r3, -4(r1)
        stw r4, -8(r1)
        lfs f0, lo16(LCPI2_0)(r2)
        lfd f1, -8(r1)
        fsub f0, f1, f0
        frsp f1, f0
        blr

This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).

llvm-svn: 26943

llvm-svn: 26813

llvm-svn: 26806

5 instructions away.

llvm-svn: 26801

llvm-svn: 26800

registers, and update it on entry to each function, then restore it on exit.

This compiles:

void func(vfloat *a, vfloat *b, vfloat *c) {
        *a = *b * *c + *c;
}

to this:

_func:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r5
        lvx v1, 0, r4
        vmaddfp v0, v1, v0, v0
        stvx v0, 0, r3
        mtspr 256, r2
        blr

GCC produces this (which has additional stack accesses):

_func:
        mfspr r0,256
        stw r0,-4(r1)
        oris r0,r0,0xc000
        mtspr 256,r0
        lvx v0,0,r5
        lvx v1,0,r4
        lwz r12,-4(r1)
        vmaddfp v0,v0,v1,v0
        stvx v0,0,r3
        mtspr 256,r12
        blr

llvm-svn: 26733

Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place.  Other methods should also be moved if anyoneis interested. :)

llvm-svn: 25913

llvm-svn: 25231

functionality change, just code cleanup.

llvm-svn: 25230

pointer in the epilog, not a load.

llvm-svn: 25229

hasInFlag, hasOutFlag.

llvm-svn: 25155

* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)

llvm-svn: 24997

alignment information appropriately.  Includes code for PowerPC to support
fixed-size allocas with alignment larger than the stack.  Support for
arbitrarily aligned dynamic allocas coming soon.

llvm-svn: 24224

llvm-svn: 23787

purely mechanical.

llvm-svn: 23778

redundant after the change.

llvm-svn: 23759

This completes the grand PPC file renaming

llvm-svn: 23745

llvm-svn: 23743

llvm-svn: 23742

llvm-svn: 23738

llvm-svn: 23581

These are used to represent float and double values, and the two regclasses
contain the same physical registers.

llvm-svn: 23577

llvm-svn: 23571

llvm-svn: 23558

llvm-svn: 23539

llvm-svn: 23374

for FP as well.  This triggers a couple dozen times on 177.mesa (for example).

llvm-svn: 23299

with copies, leading to code like this:

       lwz r4, 380(r1)
       or r10, r4, r4    ;; Last use of r4

By teaching the PPC backend how to fold spills into copies, we now get this
code:

       lwz r10, 380(r1)

wow. :)

This reduces a testcase nate sent me from 1505 instructions to 1484.

Note that this could handle FP values but doesn't currently, for reasons
mentioned in the patch

llvm-svn: 23298

llvm-svn: 23297

llvm-svn: 23105

  * avoid calling getClass() multiple times (it is relatively expensive)
  * Allow -disable-fp-elim to turn of frame pointer elimination.

llvm-svn: 23104

llvm-svn: 22913

llvm-svn: 22882

and asm printer for PowerPC if one is not specified.

llvm-svn: 22659