llvm-svn: 37705

TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704

llvm-svn: 37700

llvm-svn: 37669

llvm-svn: 37659

with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644

llvm-svn: 37643

llvm-svn: 37606

llvm-svn: 37571

llvm-svn: 37528

llvm-svn: 37527

llvm-svn: 37517

llvm-svn: 37516

Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a compilation warning? I blame it on the FE folks.

llvm-svn: 37484

llvm-svn: 37468

llvm-svn: 37437

llvm-svn: 37434

switches.  There is one really easy isel thing here with tst we are not
getting.

llvm-svn: 37400

llvm-svn: 37388

llvm-svn: 37385

llvm-svn: 37381

smaller than the preferred alignment, but so that the target can actually
specify a minimum alignment if needed.  This fixes some objc protocol
failures Devang tracked down.

llvm-svn: 37373

For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias.

llvm-svn: 37351

llvm-svn: 37349

llvm-svn: 37342

llvm-svn: 37308

llvm-svn: 37272

llvm-svn: 37271

llvm-svn: 37269

BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd.

llvm-svn: 37268

Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code.

llvm-svn: 37199

llvm-svn: 37197

llvm-svn: 37194

llvm-svn: 37193

in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm.  Ideally you would get cooperation
from the RA as well but this is not there yet.

llvm-svn: 37179

llvm-svn: 37125

llvm-svn: 37124

llvm-svn: 37120

llvm-svn: 37119

Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.

llvm-svn: 37118