with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644

llvm-svn: 37578

implementation for x86.

llvm-svn: 37576

llvm-svn: 37571

llvm-svn: 37528

llvm-svn: 37266

llvm-svn: 37193

llvm-svn: 36430

llvm-svn: 36404

llvm-svn: 35638

llvm-svn: 35616

_test3:
        leaq (,%rdi,4), %rax
        orq %rdi, %rax
        ret

instead of:
_test2:
        movq %rdi, %rax
        shlq $2, %rax
        orq %rdi, %rax
        ret

llvm-svn: 35434

system assembler not groking legal instructions like "leal (,%esi,8), %ecx".

llvm-svn: 35393

1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
   in three-address form.

This gives us asm diffs like:

-       leal (,%eax,4), %eax
+       shll $2, %eax

which is faster on some processors and smaller on all of them.

and, more interestingly:

-       movl 24(%esi), %eax
-       leal (,%eax,4), %edi
+       movl 24(%esi), %edi
+       shll $2, %edi

Without #2, #1 was a significant pessimization in some cases.

This implements CodeGen/X86/shift-codegen.ll

llvm-svn: 35204

moves, loads, etc. are recognized.

llvm-svn: 35031

llvm-svn: 33537

convertToThreeAddress() is now responsible for updating live info as well as inserting the new MI's.

llvm-svn: 32097

of opcode and number of operands.

llvm-svn: 31947

llvm-svn: 31794

llvm-svn: 31765

llvm-svn: 31712

llvm-svn: 31298

llvm-svn: 31262

llvm-svn: 31099

llvm-svn: 31097

llvm-svn: 31095

llvm-svn: 31093

llvm-svn: 31074

llvm-svn: 31065

llvm-svn: 31024

llvm-svn: 30938

llvm-svn: 30663

llvm-svn: 30177

actually *removes* one of the operands, instead of just assigning both operands
the same register.  This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.

Changing this also gets rid of a bunch of hacky code in various places.

This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.

llvm-svn: 30108

llvm-svn: 29275

llvm-svn: 28577

only transform a shufps to pshufd when the first two operands are the same.

llvm-svn: 28575

llvm-svn: 28574

llvm-svn: 28573

llvm-svn: 28565