of the instruction.

Note that this change affects the existing non-atomic load and store
instructions; the parser now accepts both forms, and the change is noted
in the release notes.

llvm-svn: 137527

Tidy up the code a bit and push the definition of the value next to the uses
to try to minimize this sort of issue from arising again while I'm at it.

rdar://9945172

llvm-svn: 137525

llvm-svn: 137521

Some reorganization of atomic docs.  Added explicit section for NonAtomic.  Added example for illegal non-atomic operation.

llvm-svn: 137520

vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.

llvm-svn: 137519

llvm-svn: 137518

llvm-svn: 137515

Partial fix for rdar://9945172.

llvm-svn: 137513

they're the correct type.

llvm-svn: 137511

Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.

llvm-svn: 137502

This implements the 'landingpad' instruction. It's used to indicate that a basic
block is a landing pad. There are several restrictions on its use (see
LangRef.html for more detail). These restrictions allow the exception handling
code to gather the information it needs in a much more sane way.

This patch has the definition, implementation, C interface, parsing, and bitcode
support in it.

llvm-svn: 137501

llvm-svn: 137499

prevailing convention.  Thanks to Dave Zarzycki for the patch.

llvm-svn: 137497

llvm-svn: 137496

Port over the basic ARM encodings test file to a decoding test file.  Greatly increases our test coverage of basic ARM-mode instructions.

llvm-svn: 137495

Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings.

llvm-svn: 137494

llvm-svn: 137489

llvm-svn: 137488

llvm-svn: 137487

llvm-svn: 137486

llvm-svn: 137485

integer register to a floating point register. It is not valid to interpret
the value of a floating pointer register as part of a double precision
floating point value after a single precision floating point computational
or move instruction stores its result to the register.

- In the test case, the following code is generated before this patch is
  applied:
mtc1  $zero, $f2    ; unformatted copy to $f2
mov.s $f0, $f2      ; $f0 is in single format
sdc1  $f12, 0($sp)
mov.s $f1, $f2      ; $f1 is in single format
c.eq.d  $f12, $f0   ; $f0 cannot be interpreted as double

- The following code is generated after this patch is applied:
mtc1  $zero, $f0    ; unformatted copy to $f0
mtc1  $zero, $f1    ; unformatted copy to $f1
c.eq.d  $f12, $f0   ; $f0 can be interpreted as double

Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and
provided the test case.

llvm-svn: 137484

llvm-svn: 137483

llvm-svn: 137482

llvm-svn: 137481

llvm-svn: 137480

llvm-svn: 137479

llvm-svn: 137478

llvm-svn: 137476

llvm-svn: 137471

llvm-svn: 137470

llvm-svn: 137468

llvm-svn: 137467

llvm-svn: 137466

llvm-svn: 137464

llvm-svn: 137463

when building with assertions disabled.

llvm-svn: 137460

llvm-svn: 137444

Thanks to Jeff Yasskin to reword.

llvm-svn: 137443

llvm-svn: 137442