Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code.

llvm-svn: 142642

block frequency analyses. This differs substantially from the existing
block-placement pass in LLVM:

1) It operates on the Machine-IR in the CodeGen layer. This exposes much
   more (and more precise) information and opportunities. Also, the
   results are more stable due to fewer transforms ocurring after the
   pass runs.
2) It uses the generalized probability and frequency analyses. These can
   model static heuristics, code annotation derived heuristics as well
   as eventual profile loading. By basing the optimization on the
   analysis interface it can work from any (or a combination) of these
   inputs.
3) It uses a more aggressive algorithm, both building chains from tho
   bottom up to maximize benefit, and using an SCC-based walk to layout
   chains of blocks in a profitable ordering without O(N^2) iterations
   which the old pass involves.

The pass is currently gated behind a flag, and not enabled by default
because it still needs to grow some important features. Most notably, it
needs to support loop aligning and careful layout of loop structures
much as done by hand currently in CodePlacementOpt. Once it supports
these, and has sufficient testing and quality tuning, it should replace
both of these passes.

Thanks to Nick Lewycky and Richard Smith for help authoring & debugging
this, and to Jakob, Andy, Eric, Jim, and probably a few others I'm
forgetting for reviewing and answering all my questions. Writing
a backend pass is *sooo* much better now than it used to be. =D

llvm-svn: 142641

llvm-svn: 142640

Clang.

llvm-svn: 142631

llvm-svn: 142630

llvm-svn: 142626

llvm-svn: 142624

Remove unused include of sys/uio.h in MemoryBuffer.cpp. It was not correctly protected by ifdef either.

llvm-svn: 142623

llvm-svn: 142622

top-down scheduling and top-down scheduling is going away.

llvm-svn: 142621

because they don't support physical register dependencies.

llvm-svn: 142620

Separate out ARM MSR instructions into M-class versions and AR-class versions.  This fixes some roundtripping failures.

llvm-svn: 142618

llvm-svn: 142615

llvm-svn: 142608

the last compiler built for the previous flavour is used for the next,
for example the Debug clang compiler was being used for the initial build
of the Release LLVM.  Flavors should be independent of each other.  This
especially matters if the compiler built for the previous flavour doesn't
actually work!

llvm-svn: 142607

AsmParser. This patch adds validation for target data layout strings upon
construction of TargetData objects. An attempt to construct a TargetData object
from a malformed string will trigger an assertion.

llvm-svn: 142605

causing one of the unit tests to infinitely loop, which resulted in the 
buildbots stalling.

llvm-svn: 142604

llvm-svn: 142593

llvm-svn: 142592

llvm-svn: 142591

llvm-svn: 142583

llvm-svn: 142582

llvm-svn: 142581

llvm-svn: 142579

In fact this commit is not intended to change anything unless you
use one of the new command line flags.

llvm-svn: 142577

compiler warnings.

llvm-svn: 142574

llvm-svn: 142573

Refactor code from inlining and globalopt that checks whether a function definition is unused, and enhance it so it can tell that functions which are only used by a blockaddress are in fact dead.  This probably doesn't happen much on most code, but the Linux kernel's _THIS_IP_ can trigger this issue with blockaddress.  (GlobalDCE can also handle the given tescase, but we only run that at -O3.)  Found while looking at PR11180.

llvm-svn: 142572

llvm-svn: 142570

llvm-svn: 142569

llvm-svn: 142567

llvm-svn: 142559

correctly in GetStringLength, fixing PR11181!

llvm-svn: 142558

llvm-svn: 142557

Patch by Pranav Bhandarkar!

llvm-svn: 142556

llvm-svn: 142550

When checking the availability of instructions using the TLI, a 'promoted'
instruction IS available. It means that the value is bitcasted to another type
for which there is an operation. The correct check for the availablity of an
instruction is to check if it should be expanded.

llvm-svn: 142542

llvm-svn: 142537

llvm-svn: 142535

Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size.

On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.

The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.

Fixes PR11087.

llvm-svn: 142530