to declare that they preserve other passes without needing to pull in
additional header file or library dependencies. Convert MachineFunctionPass
and CodeGenLICM to make use of this.

llvm-svn: 83555

llvm-svn: 83521

bugfix. The target may use virtual registers that aren't tracked for re-use but are allocated by the scavenger. The re-use algorithm needs to watch for that.

llvm-svn: 83519

llvm-svn: 83501

llvm-svn: 83500

llvm-svn: 83496

llvm-svn: 83483

llvm-svn: 83481

to finish it any time soon.  If someone's interested it, they can resurrect it from SVN history.

llvm-svn: 83480

teach it how to recognize invariant physical registers.

llvm-svn: 83476

implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.

llvm-svn: 83475

llvm-svn: 83474

a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.

eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.

ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.

llvm-svn: 83467

llvm-svn: 83437

This is not yet enabled.

llvm-svn: 83400

verbose-asm mode, print comments instead. This eliminates a non-comment
difference between verbose-asm mode and non-verbose-asm mode.

Also, factor out the relevant code out of all the targets and into
target-independent code.

llvm-svn: 83392

where the element is of a basic builtin type.  For example, to get
an i8* use getInt8PtrTy.

llvm-svn: 83379

llvm-svn: 83378

llvm-svn: 83367

Update processDebugLoc() so that it can be used to process debug info before and after printing an instruction.

llvm-svn: 83363

llvm-svn: 83362

This will be used by processDebugLoc().

llvm-svn: 83361

llvm-svn: 83356

llvm-svn: 83355

This code is not  yet enabled.

llvm-svn: 83349

Existence of a compile unit for input source file is a good indicator to check debug info's presence in a module.

llvm-svn: 83348

This can happen if debug info is processed lazily.

llvm-svn: 83347

void foo() { static int bar = 42; }
Here, foo's DIE is parent of bar's DIE.

llvm-svn: 83344

llvm-svn: 83343

spill slot. When frame references are via the frame pointer, they will be
negative, but Thumb1 load/store instructions only allow positive immediate
offsets. Instead, Thumb1 will spill to R12.

llvm-svn: 83336

llvm-svn: 83317

the new predicates I added) instead of going through a context and doing a
pointer comparison.  Besides being cheaper, this allows a smart compiler
to turn the if sequence into a switch.

llvm-svn: 83297

which causes dependence info to be linked into lli.

llvm-svn: 83289

llvm-svn: 83285

llvm-svn: 83255

llvm-svn: 83254

MI->addOperand invalidates references to it's operands, avoid touching
the operand after a new one was added.

llvm-svn: 83249

llvm-svn: 83223

Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.

llvm-svn: 83218

Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.

llvm-svn: 83215