for specifying fractional bits for fixed point conversions.

llvm-svn: 117501

llvm-svn: 117496

llvm-svn: 117495

llvm-svn: 117483

elements than the result vector type.  So, when an instruction like:

%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>

is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements.  That is:

shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]

That's probably the right thing for x86 but for NEON, we'd much rather have:

shuffle [a,b,c,d], undef

Teach the DAG combiner how to do that transformation for ARM.  Radar 8597007.

llvm-svn: 117482

llvm-svn: 117478

llvm-svn: 117475

operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.

llvm-svn: 117461

llvm-svn: 117459

llvm-svn: 117458

encoding tricks. Handle the 'imm doesn't fit in the insn' case.

llvm-svn: 117454

integer values), not with the addrmode2 encoding.

llvm-svn: 117429

doesn't need the additional addrmode2 register operand. Missed it the first
time around.

llvm-svn: 117421

rdar://8477752.

llvm-svn: 117419

llvm-svn: 117418

llvm-svn: 117411

explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409

llvm-svn: 117402

llvm-svn: 117398

llvm-svn: 117394

llvm-svn: 117388

llvm-svn: 117387

llvm-svn: 117380

llvm-svn: 117374

llvm-svn: 117348

llvm-svn: 117347

llvm-svn: 117331

the existing streamer methods that are endian safe.

llvm-svn: 117323

llvm-svn: 117315

llvm-svn: 117309

Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.

llvm-svn: 117294

llvm-svn: 117293

llvm-svn: 117291

llvm-svn: 117282

llvm-svn: 117280

llvm-svn: 117279

llvm-svn: 117276

llvm-svn: 117275

llvm-svn: 117274

llvm-svn: 117273