llvm-svn: 22848

several of the PowerPC opcodes that come in both negated and non-negated
forms.

llvm-svn: 22845

llvm-svn: 22837

incomplete, but it is a start.  It handles basic argument/retval stuff, immediates,
add and sub.

llvm-svn: 22836

llvm-svn: 22835

selector.  Also, there is no difference between addSImm and addImm, so just
use addImm, folding some branches.

llvm-svn: 22819

llvm-svn: 22818

marked as legal.

llvm-svn: 22816

llvm-svn: 22815

Remove dead code in ISD::Constant handling
Add support for add long, imm16

We now codegen 'long long foo(long long a) { return ++a; }'
as:
addic r4, r4, 1
addze r3, r3
blr

instead of:
li r2, 1
li r5, 0
addc r2, r4, r2
adde r3, r3, r5
blr

llvm-svn: 22811

llvm-svn: 22808

fixme from the PowerPC backend.  Emit slightly better code for legalizing
select_cc.

llvm-svn: 22805

can be shared with the DAG->DAG selector.

llvm-svn: 22799

Only run createLowerConstantExpressionsPass for the simple isel.  The DAG
isel has no need for it.

llvm-svn: 22794

llvm-svn: 22792

Changed code gen for int to f32 to use rounding.  This makes FP results
consistent with gcc.

llvm-svn: 22791

1. Not selecting the false value of a select_cc in the false arm, which
   isn't legal for nested selects.
2. Actually returning the node we created and Legalized in the FP_TO_UINT
   Expander.

llvm-svn: 22789

codegen for FP_TO_UINT by using the legalizer's SELECT variant.

Implement a codegen improvement for SELECT_CC, selecting the false node in
the MBB that feeds the phi node.  This allows us to codegen:
void foo(int *a, int b, int c) { int d = (a < b) ? 5 : 9; *a = d; }
as:
_foo:
        li r2, 5
        cmpw cr0, r4, r3
        bgt .LBB_foo_2  ; entry
.LBB_foo_1:     ; entry
        li r2, 9
.LBB_foo_2:     ; entry
        stw r2, 0(r3)
        blr

insted of:
_foo:
        li r2, 5
        li r5, 9
        cmpw cr0, r4, r3
        bgt .LBB_foo_2  ; entry
.LBB_foo_1:     ; entry
        or r2, r5, r5
.LBB_foo_2:     ; entry
        stw r2, 0(r3)
        blr

llvm-svn: 22784

back once a DAG->DAG ISel exists.

llvm-svn: 22778

Fix for 2005-08-12-rlwimi-crash.ll.  Make allowance for masks being shifted to
zero.

llvm-svn: 22773

1. This changes handles the cases of (~x)&y and x&(~y) yielding ANDC, and
   (~x)|y and x|(~y) yielding ORC.

llvm-svn: 22771

specified opcode and an integer constant right operand.

2. Modified ISD::SHL, ISD::SRL, ISD::SRA to use rlwinm when applied after a mask.

llvm-svn: 22761

Patch by Jim Laskey.

llvm-svn: 22760

(avoids an extra level of indirection in MakeReg).

  defined MakeIntReg using RegMap->createVirtualRegister(PPC32::GPRCRegisterClass)
  defined MakeFPReg using RegMap->createVirtualRegister(PPC32::FPRCRegisterClass)

  s/MakeReg(MVT::i32)/MakeIntReg/
  s/MakeReg(MVT::f64)/MakeFPReg/

Patch by Jim Laskey!

llvm-svn: 22759

reflects what the hardware is capable of.  This significantly simplifies
the CC handling logic throughout the ISel.

llvm-svn: 22756

1. Clean up how SelectIntImmediateExpr handles use counts.
2. "Subtract from" was not clearing hi 16 bits.

Patch by Jim Laskey

llvm-svn: 22754

Patch by Jim Laskey!

llvm-svn: 22750

  New routine: ISel::SelectIntImmediateExpr
  2. Now checking use counts of large constants.  If use count is > 2 then drop
  thru so that the constant gets loaded into a register.
  Source:

int %test1(int %a) {
entry:
       %tmp.1 = add int %a,      123456789      ; <int> [#uses=1]
       %tmp.2 = or  int %tmp.1,  123456789      ; <int> [#uses=1]
       %tmp.3 = xor int %tmp.2,  123456789      ; <int> [#uses=1]
       %tmp.4 = sub int %tmp.3, -123456789      ; <int> [#uses=1]
       ret int %tmp.4
}

Did Emit:

       .machine ppc970


       .text
       .align  2
       .globl  _test1
_test1:
.LBB_test1_0:   ; entry
       addi r2, r3, -13035
       addis r2, r2, 1884
       ori r2, r2, 52501
       oris r2, r2, 1883
       xori r2, r2, 52501
       xoris r2, r2, 1883
       addi r2, r2, 52501
       addis r3, r2, 1883
       blr


Now Emits:

       .machine ppc970


       .text
       .align  2
       .globl  _test1
_test1:
.LBB_test1_0:   ; entry
       lis r2, 1883
       ori r2, r2, 52501
       add r3, r3, r2
       or r3, r3, r2
       xor r3, r3, r2
       add r3, r3, r2
       blr

Patch by Jim Laskey!

llvm-svn: 22749

llvm-svn: 22747

llvm-svn: 22732

llvm-svn: 22729

llvm-svn: 22727

llvm-svn: 22726

code sequences.

llvm-svn: 22719

Patch by Jim Laskey.

llvm-svn: 22716

Patch by Jim Laskey!

llvm-svn: 22715

way.  This allows ORI/ORIS pairs, for example.

llvm-svn: 22714

Includes wider support for rotate and mask cases.

Patch by Jim Laskey.

I've requested that Jim add new regression tests the newly handled cases.

llvm-svn: 22712

Includes support for 32-bit constants using addi/addis.

Patch by Jim Laskey.

llvm-svn: 22711

Patch by Jim Laskey

llvm-svn: 22710