llvm-svn: 157348

Now that the coalescer keeps live intervals and machine code in sync at
all times, it needs to deal with identity copies differently.

When merging two virtual registers, all identity copies are removed
right away. This means that other identity copies must come from
somewhere else, and they are going to have a value number.

Deal with such copies by merging the value numbers before erasing the
copy instruction. Otherwise, we leave dangling value numbers in the live
interval.

This fixes PR12927.

llvm-svn: 157340

Patch by Jush Lu <jush.msn@gmail.com>.

llvm-svn: 157336

llvm-svn: 157329

Apparently LLVM only stopped emitting this after LLVM 3.0

llvm-svn: 157325

inline threshold if the global inline threshold is lower (as for -Oz).

Reviewed by Chandler Carruth and Bill Wendling.

llvm-svn: 157323

llvm-svn: 157320

llvm-svn: 157319

llvm-svn: 157317

llvm-svn: 157315

llvm-svn: 157313

case.

llvm-svn: 157312

llvm-svn: 157309

Part of rdar://11496790

llvm-svn: 157303

teach computeAllocSize about realloc, reallocf, and valloc

llvm-svn: 157298

llvm-svn: 157292

llvm-svn: 157274

llvm-svn: 157273

llvm-svn: 157264

Fixes PR12898: SCEVExpander crash.

llvm-svn: 157263

move EmitGEPOffset from InstCombine to Transforms/Utils/Local.h

(a draft of this) patch reviewed by Andrew, thanks.

llvm-svn: 157261

After a lot of discussion, we realized it's not the best option for run-time bounds checking

llvm-svn: 157255

Also make sure registers aren't erased twice if the dead def mentions
the register twice.

This fixes PR12911.

llvm-svn: 157254

leader table.  That's because it wasn't expecting instructions to turn up as
leader for a value number that is not its own, but equality propagation could
create this situation.  One solution is to have the leader table use a WeakVH
but this slows down GVN by about 5%.  Instead just have equality propagation not
add instructions to the leader table, only constants and arguments.  In theory
this might cause GVN to run more (each time it changes something it runs again)
but it doesn't seem to occur enough to cause a slow down.

llvm-svn: 157251

Fix constant used for pshufb mask when lowering v16i8 shuffles. Bug introduced in r157043. Fixes PR12908.

llvm-svn: 157236

instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.

llvm-svn: 157234

32-bit offset jump tables just use real branch instructions and so aren't
marked as data regions. We were still emitting the .end_data_region
marker though, which assert()ed.

rdar://11499158

llvm-svn: 157221

llvm-svn: 157218

Fix use of an unitialized value in the LegalizeOps expansion for ISD::SUB.  No in-tree targets exercise this path.

Patch by Micah Villmow.

llvm-svn: 157215

t2RSB defined the operand correctly, but tRSBS didn't.

llvm-svn: 157200

llvm-svn: 157197

llvm-svn: 157195

Patch by Jose Fonseca.

llvm-svn: 157191

PR1255 (case ranges: work with ConstantRangesSet instead of ConstantInt) related changes for Execution and Verifier.

llvm-svn: 157183

Allow 256-bit shuffles to still be split even if only half of the shuffle comes from two 128-bit pieces.

llvm-svn: 157175

This helps compile time when the greedy register allocator splits live
ranges in giant functions. Without the bias, we would try to grow
regions through the giant edge bundles, usually to find out that the
region became too big and expensive.

If a live range has many uses in blocks near the giant bundle, the small
negative bias doesn't make a big difference, and we still consider
regions including the giant edge bundle.

Giant edge bundles are usually connected to landing pads or indirect
branches.

llvm-svn: 157174

With physreg joining out of the way, it is easy to recognize the
instructions that need their kill flags cleared while testing for
interference.

This allows us to skip the final scan of all instructions for an 11%
speedup of the coalescer pass.

llvm-svn: 157169

It can sometimes be used in addressing modes that don't support %ESP.

llvm-svn: 157165

It can be necessary to restrict to a sub-class before accessing
sub-registers.

llvm-svn: 157164

When rewriting operands, make sure the new registers have a compatible
register class.

llvm-svn: 157163