as setcc and select next.

llvm-svn: 23295

llvm-svn: 23294

only add a reload live range once for the instruction.  This is one step
towards fixing a regalloc pessimization that Nate notice, but is later undone
by the spiller (so no code is changed).

llvm-svn: 23293

is zero.  This lets the register allocator elide some copies in some cases.

This implements CodeGen/PowerPC/rlwimi-commute.ll

llvm-svn: 23292

llvm-svn: 23291

llvm-svn: 23290

llvm-svn: 23289

definitions are void

llvm-svn: 23288

llvm-svn: 23287

1. Add support for defining Pattern's, which can match expressions when there
   is no instruction that directly implements something.  Instructions usually
   implicitly define patterns.
2. Add support for defining SDNodeXForm's, which are node transformations.
   This seperates the concept of a node xform out from the existing predicate
   support.

Using this new stuff, we add a few instruction patterns, one for testing, and
two for OR/XOR by an arbitrary immediate.

llvm-svn: 23286

llvm-svn: 23285

constraints defined in the DAG node definitions in the .td files.  This
allows us to infer (and check!) the types for all nodes in the current
ppc .td file.  For example, instead of:

Inst pattern EQV:       (set GPRC:i32:$rT, (xor (xor GPRC:i32:$rA, GPRC:i32:$rB), (imm)<<Predicate_immAllOnes>>))

we now fully infer:

Inst pattern EQV:       (set:void GPRC:i32:$rT, (xor:i32 (xor:i32 GPRC:i32:$rA, GPRC:i32:$rB), (imm:i32)<<Predicate_immAllOnes>>))

from:  (set GPRC:$rT, (not (xor GPRC:$rA, GPRC:$rB)))
llvm-svn: 23284

llvm-svn: 23283

llvm-svn: 23282

llvm-svn: 23281

llvm-svn: 23280

llvm-svn: 23279

llvm-svn: 23278

the rest of the instructions, add comment markers to seperate portions of
the file into logical parts

llvm-svn: 23277

llvm-svn: 23276

llvm-svn: 23275

This implements Regression/TableGen/AnonDefinitionOnDemand.td

llvm-svn: 23274

llvm-svn: 23273

llvm-svn: 23272

llvm-svn: 23271

llvm-svn: 23270

(set GPRC:i32:$rD, (add GPRC:i32:$rA, (imm)<<Predicate_immSExt16>>:$imm))

not:

(set GPRC:i32:$rD, (add GPRC:i32:$rA, (imm)<<Predicate_immSExt16>>))

(we keep the ":$imm")

llvm-svn: 23269

llvm-svn: 23268

for matching signed 16-bit and shifted 16-bit ppc immediates

llvm-svn: 23267

llvm-svn: 23266

llvm-svn: 23265

llvm-svn: 23264

llvm-svn: 23263

llvm-svn: 23262

progress.  It correctly parses instructions and pattern fragments and glues
together pattern fragments into instructions.

The only code it generates currently is some boilerplate code for things
like the EntryNode.

llvm-svn: 23261

as well as fixing how we replace old values with new values.

llvm-svn: 23260

preserve livevar

llvm-svn: 23259

This restores all of stanford to being identical with and without the dag
combiner with the add folding turned off in sd.cpp.

llvm-svn: 23258

'' is not a recognized processor for this target (ignoring processor)

Default to "generic" instead of "" for the default CPU.

llvm-svn: 23257

'' is not a recognized processor for this target (ignoring processor)

instead of:

 is not a recognized processor for this target (ignoring processor)

llvm-svn: 23256