llvm-svn: 102493

llvm-svn: 101979

a new subtarget option for AES and check for the support.  Add "westmere"
line of processors and add AES-NI support to the core i7.

Add a couple of TODOs for information I couldn't verify.

llvm-svn: 100231

llvm-svn: 100089

llvm-svn: 98810

PR4841.  Patch by Craig Smith!

llvm-svn: 98496

llvm-svn: 97427

llvm-svn: 95981

llvm-svn: 93235

to not touch Cygwin: the change caused llvm-gcc build failures due to
long double getting the wrong size.  Patch by Aaron Gray.

llvm-svn: 93234

Implement a feature (-vector-unaligned-mem) to allow targets to
ignore alignment requirements for SIMD memory operands.  This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.

llvm-svn: 93151

Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.

llvm-svn: 91910

Based on patch by Michael Beck!

llvm-svn: 91745

be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0

llvm-svn: 91672

and support for blockaddresses in x86-32 PIC mode.

llvm-svn: 89506

llvm-svn: 88682

llvm-svn: 86634

Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies. 

llvm-svn: 86628

Please verify.

llvm-svn: 86397

llvm-svn: 84931

Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.

llvm-svn: 84911

llvm-svn: 84431

llvm-svn: 84425

stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot 
move above a store of spill slot #2. 
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.

llvm-svn: 84424

llvm-svn: 84273

llvm-svn: 84200

the global variable list only happen for COFF targets.

llvm-svn: 82010

llvm-svn: 80892

X86JITInfo::getLazyResolverFunction() should not read cpu id to determine whether sse is available. Just use consult subtarget.

No functionality changes.

llvm-svn: 80880

conditional moves as a subtarget feature.  This is the easy part of 
PR4841.

llvm-svn: 80763

instead of X86 Subtarget.  This elimianates dependencies on
X86Subtarget from X86TAI.

llvm-svn: 78746

Module*.

Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.

llvm-svn: 77918

llvm-svn: 75276

llvm-svn: 75275

add a couple of predicates to test for "stub style pic in PIC mode" and "stub style pic in dynamic-no-pic" mode.

llvm-svn: 75273

elimiantes the last use of GVRequiresExtraLoad, so delete it.

llvm-svn: 75244

need for other purposes.

llvm-svn: 75243

is just a trivial wrapper around "ClassifyGlobalReference", which
stole a ton of logic from LowerGlobalAddress.

llvm-svn: 75237

llvm-svn: 75232

more complex and slow than just directly testing what we care about.

llvm-svn: 75231