- Add AVX SSE2 Move doubleword and quadword instructions.
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.

llvm-svn: 107365

llvm-svn: 107308

llvm-svn: 107306

llvm-svn: 107300

llvm-svn: 107293

llvm-svn: 107280

llvm-svn: 107246

llvm-svn: 107245

llvm-svn: 107243

llvm-svn: 107241

llvm-svn: 107240

- Add VEX encoding bits to x86 MRM0r-MRM7r

llvm-svn: 107238

llvm-svn: 107225

llvm-svn: 107211

llvm-svn: 107206

Add AVX ld/st XCSR register.
Add VEX encoding bits for MRMXm x86 form

llvm-svn: 107204

llvm-svn: 107178

llvm-svn: 107168

llvm-svn: 107166

llvm-svn: 107130

llvm-svn: 107116

llvm-svn: 107108

llvm-svn: 107067

llvm-svn: 106944

CopyFromReg nodes for aliasing registers (AX and AL). This confuses the fast
register allocator.

Instead of CopyFromReg(AL), use ExtractSubReg(CopyFromReg(AX), sub_8bit).

This fixes PR7312.

llvm-svn: 106934

llvm-svn: 106917

Add several AVX MOV flavors
Support VEX encoding for MRMDestReg

llvm-svn: 106912

llvm-svn: 106906

Support VEX encoding for MRMDestReg

llvm-svn: 106896

for an "i" constraint should get lowered; PR 6309.  While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.

llvm-svn: 106893

llvm-svn: 106886

- 2010-06-25-CoalescerSubRegDefDead.ll is the testcase for r106878.

llvm-svn: 106880

llvm-svn: 106877

llvm-svn: 106876

Refactoring of more SSE conversion instructions. Also add some AVX instrinsics Int_V... placeholders

llvm-svn: 106867

llvm-svn: 106815

llvm-svn: 106808

llvm-svn: 106804

llvm-svn: 106796

- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.

llvm-svn: 106787