implementing rdar://8431864

llvm-svn: 118364

different forms of this instruction (movw/movl/movq) which we reported
as being ambiguous.  Since they all do the same thing, gas just picks the
one with the shortest encoding.  Follow its lead here.

This implements rdar://8208615

llvm-svn: 118362

llvm-svn: 118361

llvm-svn: 118358

exposed:

GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.

Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).

As such, switch the canonical form of this instruction to "pi" instead
of "ip".  This makes the code generator and disassembler generate pi,
avoiding the gas bug.

llvm-svn: 118356

shift-by-1 instructions, where the asmstring doesn't contain
the implicit 1.  It turns out that a bunch of these rotate
instructions were completely broken because they used 1 
instead of $1.

This fixes assembly mismatches on "rclb	$1, %bl" and friends,
where we used to generate the 3 byte form, we now generate the
proper 2-byte form.

llvm-svn: 118355

listed in its asm string, for consistency with the other similar
instructions.

llvm-svn: 118354

llvm-svn: 118353

fixed physical registers.  Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).

llvm-svn: 118352

add fixed immediate values.  Move the aad and aam aliases to
use this, and document it.

llvm-svn: 118350

llvm-svn: 118349

llvm-svn: 118348

llvm-svn: 118347

floating point stack instructions instead of looking for b/w/l/q.

This fixes issues where we'd accidentally match fistp to fistpl,
when it is in fact an ambiguous instruction.

This changes the behavior of llvm-mc to reject fstp, which was the
correct fix for rdar://8456389:
t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt')
fstp	(%rax)

it also causes us to correctly reject fistp and fist, which addresses
PR8528:

t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl')
fistp (%rax)
^
t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl')
fist (%rax)
^

Thanks to Ismail Donmez for tracking down the issue here!

llvm-svn: 118346

result instruction operand numbering matched the result pattern.

Fixing this allows us to move the xchg/test aliases to the .td file.

llvm-svn: 118334

llvm-svn: 118332

tidy up the movsx and movzx aliases.

llvm-svn: 118331

from c++ hacks to proper .td InstAlias definitions.  Change them!

llvm-svn: 118330

operand list instead of the operand list redundantly declared on the alias
or instruction.

With this change, we finally remove the ins/outs list on the alias.  Before:
  def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
                  "movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
  def : InstAlias<"movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;

This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.

llvm-svn: 118329

llvm-svn: 118288

sequence of loads and stores was being generated to perform the
copy on the x86 targets if the parameter was less than 4 byte
aligned, causing llc to use up vast amounts of memory and time.
Use a "rep movs" form instead.  PR7170.

llvm-svn: 118260

and as such can be represented by an MVT - the more complicated
EVT is not needed.  Use MVT for ValVT everywhere.

llvm-svn: 118245

with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.

llvm-svn: 118169

value type, so there is no point in passing it around using
an EVT.  Use the simpler MVT everywhere.  Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.

llvm-svn: 118167

llvm-svn: 117967

from X86AsmParser.cpp

llvm-svn: 117952

must be 8 bits.  Support this memory form.

llvm-svn: 117902

aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.

llvm-svn: 117901

in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.

llvm-svn: 117897

various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.

llvm-svn: 117884

Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862

and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.

llvm-svn: 117861

how the push/pop mnemonic aliases are wrong.

llvm-svn: 117857

calling convention out of the fast and normal ISel files, and
into the calling convention TD file.

llvm-svn: 117856

which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.

llvm-svn: 117855

"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.

llvm-svn: 117831

directives, allowing things like this:

def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;

Move the rest of the X86 MnemonicAliases over to the .td file.

llvm-svn: 117830

llvm-svn: 117824

llvm-svn: 117823

llvm-svn: 117822