llvm-svn: 86471

llvm-svn: 86470

llvm-svn: 86469

llvm-svn: 86468

llvm-svn: 86466

code miscompilation

llvm-svn: 86463

this gives llvm-gcc generated modules the right data.

llvm-svn: 86435

Use aligned load/store instructions for spilling Q registers when we know the stack slot is 128 bit aligned

llvm-svn: 86425

llvm-svn: 86423

1. rename the movhp patfrag to movlhps, since thats what it actually matches
2. eliminate the bogus movhps load and store patterns, they were incorrect.  The load transforms are already handled (correctly) by shufps/unpack.
3. revert a recent test change to its correct form.

llvm-svn: 86415

llvm-svn: 86408

llvm-svn: 86404

llvm-svn: 86403

llvm-svn: 86400

Please verify.

llvm-svn: 86397

llvm-svn: 86386

llvm-svn: 86385

llvm-svn: 86384

llvm-svn: 86383

llvm-svn: 86382

llvm-svn: 86381

llvm-svn: 86380

llvm-svn: 86379

Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.

llvm-svn: 86375

datatypes on a given CPU.  This is intended to allow instcombine and other
transformations to avoid converting big sequences of operations to an
inconvenient width, and will help clean up after SRoA.  See also "Adding 
legal integer sizes to TargetData" on Feb 1, 2009 on llvmdev, and PR3451.

Comments welcome.

llvm-svn: 86370

llvm-svn: 86369

llvm-svn: 86367

llvm-svn: 86366

MachineRelocations, "stub" always refers to a far-call stub or a
load-a-faraway-global stub, so this patch adds "Far" to the term. (Other stubs
are used for lazy compilation and dlsym address replacement.) The variable was
also inconsistent between the positive and negative sense, and the positive
sense ("NeedStub") was more demanding than is accurate (since a nearby-enough
function can be called directly even if the platform often requires a stub).
Since the negative sense causes double-negatives, I switched to
"MayNeedFarStub" globally.

llvm-svn: 86363

of movhps as the constraint.  Changes optimizations so
update testcases as appropriate as well.

llvm-svn: 86360

llvm-svn: 86332

llvm-svn: 86330

  except it doesn't care if the definitions' virtual registers differ. This is
  used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
  Since pc relative constantpool entries are always different, this requires it
  it check if the values can actually the same.

llvm-svn: 86328

llvm-svn: 86325

Add code to check at SelectionDAGISel::LowerArguments time to see if return values can be lowered to registers.  Coming soon, code to perform sret-demotion if return values cannot be lowered to registers

llvm-svn: 86324

was wrong and too aggressive in the sense that DPSoRegFrm includes both constant
shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and
Inst{7} = 0).  The 'rr' fragment of the multiclass definitions actually means
register/register with no shift, see A8-11.

llvm-svn: 86319

llvm-svn: 86310

  load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.

llvm-svn: 86304

llvm-svn: 86303

will not accept negative values for these.  LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates.  Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.

llvm-svn: 86301