Commits · 058190507bb19c3fcc1832d239b47ca07c1da921 · Roger Ferrer / llvm-epi-0.8

Oct 21, 2010
- Add encodings for movement between ARM core registers and single-precision · 05819050
  Bill Wendling authored Oct 20, 2010
```
registers.

llvm-svn: 116961
```
  05819050
- Fix crash introduced in 116852. 8573915. · ff37675c
  Dale Johannesen authored Oct 20, 2010
```
llvm-svn: 116955
```
  ff37675c
Oct 20, 2010
- Remove remaining uses of ATTRIBUTE_UNUSED on variables, and delete three · 1898262a
  Chandler Carruth authored Oct 20, 2010
```
#includes in the process.

llvm-svn: 116919
```
  1898262a
- Fix a TODO by removing some unnecesary copies. · af719ef8
  Eric Christopher authored Oct 20, 2010
```
llvm-svn: 116915
```
  af719ef8
- Fix backwards conditional. · 723159ef
  Jim Grosbach authored Oct 20, 2010
```
llvm-svn: 116897
```
  723159ef
- Add dynamic realignment when rematerializing the base register. · cb6fc2b2
  Jim Grosbach authored Oct 20, 2010
```
llvm-svn: 116886
```
  cb6fc2b2
- Nuke a commented out bit that got missed a while back. · f99ee7cd
  Jim Grosbach authored Oct 19, 2010
```
llvm-svn: 116883
```
  f99ee7cd
- Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any · bbdc5d2e
  Jim Grosbach authored Oct 19, 2010
```
setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268

llvm-svn: 116879
```
  bbdc5d2e
Oct 19, 2010
- Update comments to remove obsolete references. · 3ed6338f
  Jim Grosbach authored Oct 19, 2010
```
llvm-svn: 116863
```
  3ed6338f
- Enable using vdup for vector constants which are splat of · 710a2d9d
  Dale Johannesen authored Oct 19, 2010
```
integers by default, and remove the controlling flag, now
that LICM will hoist such vdup's.  8003375.

llvm-svn: 116852
```
  710a2d9d
- Re-enable register pressure aware machine licm with fixes. Hoist() may have · 63c7608c
  Evan Cheng authored Oct 19, 2010
```
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.

llvm-svn: 116845
```
  63c7608c
- Revert r116781 "- Add a hook for target to determine whether an instruction def · 418204e5
  Daniel Dunbar authored Oct 19, 2010
```
is", which breaks some nightly tests.

llvm-svn: 116816
```
  418204e5
- - Add a hook for target to determine whether an instruction def is · 8249dfe6
  Evan Cheng authored Oct 19, 2010
```
  "long latency" enough to hoist even if it may increase spilling. Reloading
  a value from spill slot is often cheaper than performing an expensive
  computation in the loop. For X86, that means machine LICM will hoist
  SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
  instructions.
- Enable register pressure aware machine LICM by default.

llvm-svn: 116781
```
  8249dfe6
- Support alignment for NEON vld-lane and vst-lane instructions. · b6d61dc2
  Bob Wilson authored Oct 19, 2010
```
llvm-svn: 116776
```
  b6d61dc2
- ARM encoding information for [SU]SAT* instructions. · 1c6fd774
  Jim Grosbach authored Oct 18, 2010
```
llvm-svn: 116768
```
  1c6fd774
- Revert r116220 - thus turning arm fast isel back on by default. · 7b92c2a9
  Eric Christopher authored Oct 18, 2010
```
llvm-svn: 116762
```
  7b92c2a9
Oct 18, 2010
- Don't recompute MachineRegisterInfo in the Optimize* method. · 337a3113
  Bill Wendling authored Oct 18, 2010
```
llvm-svn: 116750
```
  337a3113
- For Thumb2, try to use frame pointer references for stack slots even when a · 6706f3c4
  Jim Grosbach authored Oct 18, 2010
```
base register is available. rdar://8525298

llvm-svn: 116729
```
  6706f3c4
- ARM addrmode4 instructions (ldm, stm and friends) can't encode an immediate · 00fe92da
  Jim Grosbach authored Oct 18, 2010
```
offset for stack references. Make sure we take that into account when
deciding whether to reserver an emergency spill slot for the register
scavenger. rdar://8559625

llvm-svn: 116714
```
  00fe92da
- Grammar tweak. · e8a0eaaf
  Jim Grosbach authored Oct 18, 2010
```
llvm-svn: 116712
```
  e8a0eaaf
- Remove the check for invalid calling conventions. Testing shows that they're · 167a7002
  Eric Christopher authored Oct 18, 2010
```
working just fine.

llvm-svn: 116698
```
  167a7002
- Lift arg promotion from the X86 backend. This should be unified at some point. · c103c668
  Eric Christopher authored Oct 18, 2010
```
llvm-svn: 116694
```
  c103c668
Oct 17, 2010
- Now that we handle all allocas via a non-SP reg offset remove all of the · a8a9f3c5
  Eric Christopher authored Oct 17, 2010
```
special case handling for ARM::SP.

llvm-svn: 116688
```
  a8a9f3c5
- Allow more load types to be materialized through the allocas. · 730764da
  Eric Christopher authored Oct 17, 2010
```
llvm-svn: 116683
```
  730764da
- Optimize GEP off of intermediate allocas. · d265b3fc
  Eric Christopher authored Oct 17, 2010
```
llvm-svn: 116681
```
  d265b3fc
- Fix comment. · a0b9c2e9
  Eric Christopher authored Oct 17, 2010
```
llvm-svn: 116680
```
  a0b9c2e9
- Turn on AddOperator folding in GEP. · abc3a9d3
  Eric Christopher authored Oct 17, 2010
```
llvm-svn: 116679
```
  abc3a9d3
- Use the i12 immediate versions of the load instructions - they're handled · 947e422c
  Eric Christopher authored Oct 17, 2010
```
more in the post-passes.

llvm-svn: 116678
```
  947e422c
Oct 16, 2010
- Add a MCObjectFormat class so that code common to all targets that use a · 4262a222
  Rafael Espindola authored Oct 16, 2010
```
single object format can be shared.

This also adds support for

mov zed+(bar-foo), %eax

on ELF and COFF targets.

llvm-svn: 116675
```
  4262a222
- Fix some funky formatting that got through. · c918d550
  Eric Christopher authored Oct 16, 2010
```
llvm-svn: 116653
```
  c918d550
- ARMCodeEmitter::emitMiscInstruction is dead. Long live · 5f5b922e
  Bill Wendling authored Oct 15, 2010
```
ARMCodeEmitter::emitMiscInstruction!

llvm-svn: 116644
```
  5f5b922e
- Make sure offset is 0 for load/store register to the stack call. · f410acbb
  Eric Christopher authored Oct 15, 2010
```
llvm-svn: 116640
```
  f410acbb
- Formatting. · d2466687
  Eric Christopher authored Oct 15, 2010
```
llvm-svn: 116635
```
  d2466687
- Fix else if -> if in store machinery. · a3e64c17
  Eric Christopher authored Oct 15, 2010
```
llvm-svn: 116628
```
  a3e64c17
Oct 15, 2010
- Reformatting. No functionalogicality changes. · 399add01
  Bill Wendling authored Oct 15, 2010
```
llvm-svn: 116625
```
  399add01
- Refactor ARM fast-isel reg + offset to be a base + offset. · a9b3901b
  Eric Christopher authored Oct 15, 2010
```
llvm-svn: 116622
```
  a9b3901b
- Encoding information for the various ARM saturating add/sub instructions. · 90f74fe1
  Jim Grosbach authored Oct 15, 2010
```
llvm-svn: 116612
```
  90f74fe1
- ARM binary encoding information for RSB and RSC instructions. · 00ce8dea
  Jim Grosbach authored Oct 15, 2010
```
llvm-svn: 116604
```
  00ce8dea
- Don't mark argument value stores as immutable, as otherwise the post-RA · 2d00b1b2
  Jim Grosbach authored Oct 15, 2010
```
scheduler may reorder loads from them before the stores and other such
badness. PR8347. Patch by David Meyer

llvm-svn: 116602
```
  2d00b1b2
- Use simple RegState::Define flag instead of getDefRegState(true). · f1b3681e
  Bob Wilson authored Oct 15, 2010
```
llvm-svn: 116601
```
  f1b3681e