Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.

llvm-svn: 85965

llvm-svn: 85952

llvm-svn: 85914

llvm-svn: 85878

between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.

llvm-svn: 85874

llvm-svn: 85871

llvm-svn: 85870

llvm-svn: 85869

llvm-svn: 85861

llvm-svn: 85850

llvm-svn: 85847

constant pool so they don't get wrapped separately.

llvm-svn: 85844

llvm-svn: 85824

have been passed as a reference.

llvm-svn: 85823

llvm-svn: 85809

llvm-svn: 85808

llvm-svn: 85806

llvm-svn: 85805

llvm-svn: 85798

llvm-svn: 85797

llvm-svn: 85787

llvm-svn: 85767

Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364.

PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766

llvm-svn: 85765

Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)

llvm-svn: 85764

llvm-svn: 85746

llvm-svn: 85743

llvm-svn: 85698

them for scalar floating point operations for now.

llvm-svn: 85697

llvm-svn: 85687

llvm-svn: 85685

is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.

llvm-svn: 85675

It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.

llvm-svn: 85643

Daniel Dunbar.
- Reordered the fields in the ARMOperand Mem struct to make the struct smaller.
Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each
other.
- Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments.
- Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and
added the bool ParseWriteBack parameter.
- Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister().
- Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a
memory operand.  And use it for both parsing both preindexed and post indexing
addressing forms in ARMAsmParser::ParseMemory.
- Changed the first argument to ParseShift() to a reference.
- Changed ParseShift() to check for Rrx first and return to reduce nesting.

llvm-svn: 85632

llvm-svn: 85624

llvm-svn: 85610

void f (int a1, int a2, int a3, int a4, int a5,...)

In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.

llvm-svn: 85590

clang/test/CodeGen/indirect-goto.c runs! (unoptimized)

llvm-svn: 85577

llvm-svn: 85546

bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517