llvm-svn: 103327

llvm-svn: 103325

llvm-svn: 103318

and not the real problem itself, by dropping debug info for i128 values.
rdar://7958162.

llvm-svn: 103310

wider than 64 bits.

llvm-svn: 103309

llvm-svn: 103305

llvm-svn: 103304

llvm-svn: 103303

external and the item to be relocated should not have the address of the
symbol added in.

llvm-svn: 103302

llvm-svn: 103300

getConstantFP to accept the two supported long double
target types.  This was not the original intent, but
there are other places that assume this works and it's
easy enough to do.

llvm-svn: 103299

llvm-svn: 103295

whether the extract instructions are available.

rdar://7956878

llvm-svn: 103277

llvm-svn: 103276

llvm-svn: 103272

llvm-svn: 103271

llvm-svn: 103269

patch by Peter Housel!

llvm-svn: 103267

llvm-svn: 103266

llvm-svn: 103264

DebugInfoFinder and iterates over all the contents calling print.

llvm-svn: 103262

llvm-svn: 103261

as MachineSink, but it isn't constrained by MachineInstr-level details.

llvm-svn: 103257

methods, and add dump functions implemented in terms of the print.

llvm-svn: 103254

Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise.

llvm-svn: 103235

Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values.

llvm-svn: 103234

llvm-svn: 103233

instruction, rather than a location near where the new instruction
is being inserted.

llvm-svn: 103232

lowered copies.

llvm-svn: 103228

llvm-svn: 103227

increase in the debug line info section, and it's causing
regressions in a gdb testsuite.

llvm-svn: 103226

Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers.

llvm-svn: 103218

 - This fixes "leal 0, %eax", for example.

llvm-svn: 103205

llvm-svn: 103199

and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196

we don't currently support relaxing them.

llvm-svn: 103195

doesn't have to guess.

llvm-svn: 103194

llvm-svn: 103193

llvm-svn: 103185

(replacing the previous patch for the same issue).

llvm-svn: 103183