llvm-svn: 34940

llvm-svn: 32492

can in 32-bit mode we can choose to optionally *use* 64-bit registers.

llvm-svn: 28824

llvm-svn: 28378

llvm-svn: 28368

llvm-svn: 26805

llvm-svn: 26720

1. Use flags on the instructions in the .td file to indicate the PPC970 unit
   type instead of a table in the .cpp file.  Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
   algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
   accurately.

llvm-svn: 26719

but I don't know what other PPC impls do.  If someone could update the proc
table, I would appreciate it :)

llvm-svn: 26421

llvm-svn: 25678

llvm-svn: 24012

llvm-svn: 23906

future.

llvm-svn: 23902

llvm-svn: 23892

to group appropriately and provide cues to maintainers that the lists don't
need to be ordered.

llvm-svn: 23880

llvm-svn: 23878

llvm-svn: 23870

Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.

llvm-svn: 23830

llvm-svn: 23740

llvm-svn: 23738

We will decide with subtarget support whether we ever use an i64 register
class.

llvm-svn: 23734

llvm-svn: 18982

llvm-svn: 18169

llvm-svn: 16977

llvm-svn: 15850

* Wrap long line to 80 cols

llvm-svn: 15630

Changes commited for Nate Begeman:

Use a PowerPC specific prolog epilog inserter to control where spilled
callee save regs are placed on the stack.
Get rid of implicit return address stack slot, save return address reg
(LR) in appropriate slot
Improve code generated for functions that don't have calls or access
globals


Note from Chris: PowerPCPEI will eventually be eliminated, once the
functionality is merged into CodeGen/PrologEpilogInserter.cpp

llvm-svn: 15536

llvm-svn: 15346

* PowerPCReg.td => PowerPCRegisterinfo.td
* PowerPCInstrs.td => PowerPCInstrInfo.td

llvm-svn: 15295

llvm-svn: 15271

llvm-svn: 14283

llvm-svn: 12726

llvm-svn: 11957

llvm-svn: 11834

llvm-svn: 11828