llvm-svn: 41733

Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.

llvm-svn: 39816

llvm-svn: 34668

Nicolas Geoffray!

llvm-svn: 34574

llvm-svn: 32333

llvm-svn: 31776

pair for cleanliness.  Add instructions for PPC32 preinc-stores with commented
out patterns.  More improvement is needed to enable the patterns, but we're
getting close.

llvm-svn: 31749

Ptrdist/anagram among others.

llvm-svn: 31708

llvm-svn: 29140

into i16/i32 load/stores.

llvm-svn: 29089

_foo2:
        extsw r2, r3
        std r2, -8(r1)
        lfd f0, -8(r1)
        fcfid f0, f0
        frsp f1, f0
        blr

instead of this:

_foo2:
        lis r2, ha16(LCPI2_0)
        lis r4, 17200
        xoris r3, r3, 32768
        stw r3, -4(r1)
        stw r4, -8(r1)
        lfs f0, lo16(LCPI2_0)(r2)
        lfd f1, -8(r1)
        fsub f0, f1, f0
        frsp f1, f0
        blr

This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).

llvm-svn: 26943

llvm-svn: 26722

llvm-svn: 26721

1. Use flags on the instructions in the .td file to indicate the PPC970 unit
   type instead of a table in the .cpp file.  Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
   algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
   accurately.

llvm-svn: 26719

llvm-svn: 26710

llvm-svn: 26608

llvm-svn: 26595

llvm-svn: 26594

llvm-svn: 26591

a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%).

llvm-svn: 26590

llvm-svn: 26588

flushes

llvm-svn: 26587