llvm-svn: 41808

llvm-svn: 41318

llvm-svn: 35530

llvm-svn: 35334

llvm-svn: 35330

llvm-svn: 34101

llvm-svn: 34081

llvm-svn: 33709

llvm-svn: 33630

llvm-svn: 33333

The algorithm it used before wasn't 100% correct, we now use an iterative
expansion model.  This fixes assembler errors when compiling 403.gcc with
tail merging enabled.

Change the way the branch selector works overall: Now, the isel generates
PPC::BCC instructions (as it used to) directly, and these BCC instructions
are emitted to the output or jitted directly if branches don't need
expansion.  Only if branches need expansion are instructions rewritten
and created.  This should make branch select faster, and eliminates the
Bxx instructions from the .td file.

llvm-svn: 31837

llvm-svn: 31617

llvm-svn: 31506

llvm-svn: 31236

        cmpw cr0, r7, r3
        ble cr0, LBB1_5 ;bb25
LBB1_8: ;bb17
        cmpw cr0, r8, r5
        bgt cr0, LBB1_2 ;bb

which is just as good as crnand.

llvm-svn: 31235

llvm-svn: 30937

llvm-svn: 30577

llvm-svn: 30518

llvm-svn: 30512

1. Codegen this comparison:
     if (X == 0x8000)

as:

        cmplwi cr0, r3, 32768
        bne cr0, LBB1_2 ;cond_next

instead of:

        lis r2, 0
        ori r2, r2, 32768
        cmpw cr0, r3, r2
        bne cr0, LBB1_2 ;cond_next


2. Codegen this comparison:
      if (X == 0x12345678)

as:

        xoris r2, r3, 4660
        cmplwi cr0, r2, 22136
        bne cr0, LBB1_2 ;cond_next

instead of:

        lis r2, 4660
        ori r2, r2, 22136
        cmpw cr0, r3, r2
        bne cr0, LBB1_2 ;cond_next

llvm-svn: 30509

llvm-svn: 30508

llvm-svn: 30377

llvm-svn: 29139

into i16/i32 load/stores.

llvm-svn: 29089

llvm-svn: 28355

llvm-svn: 28172

llvm-svn: 28170

llvm-svn: 28169

llvm-svn: 28168

llvm-svn: 28162

llvm-svn: 28118

llvm-svn: 27654

llvm-svn: 27360

llvm-svn: 27168

llvm-svn: 27109

llvm-svn: 27077

llvm-svn: 27000

llvm-svn: 26944

llvm-svn: 26924

llvm-svn: 26912