llvm-svn: 42282

1.
[(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 (modify EFLAGS)]
This indicates the source pattern expects the instruction would produce 2 values. The first is the result of the addition. The second is an implicit definition in register EFLAGS.
2.
def : Pat<(parallel (addc GR32:$src1, GR32:$src2), (modify EFLAGS)), ()>
Similar to #1 except this is used for def : Pat patterns.

llvm-svn: 41897

Lots of problems yet but some simple things work.

llvm-svn: 40847

llvm-svn: 40516

llvm-svn: 39921

X86 32 bits.

llvm-svn: 36283

llvm-svn: 33537

stores.

llvm-svn: 31735

llvm-svn: 31596

llvm-svn: 31576

llvm-svn: 31210

llvm-svn: 30945

llvm-svn: 30891

llvm-svn: 30878

llvm-svn: 30844

extra operand to LOADX to specify the exact value extension type.

llvm-svn: 30714

llvm-svn: 28798

x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947

llvm-svn: 27843

llvm-svn: 27834

bitconverted from some other type.

llvm-svn: 27724

llvm-svn: 27303

Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value.  Split them into separate enums.

llvm-svn: 27201

llvm-svn: 27166

llvm-svn: 27148

llvm-svn: 27132

llvm-svn: 27100

llvm-svn: 27073

llvm-svn: 27070

llvm-svn: 26911

llvm-svn: 26895

llvm-svn: 26891

llvm-svn: 26789

llvm-svn: 26649

llvm-svn: 26640

llvm-svn: 26479

and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255

llvm-svn: 26250

llvm-svn: 26249

'fpimm' in .td files is now TargetConstantFP.

llvm-svn: 25771