The MachO back-end needs to emit the garbage collection flags specified in the
module flags. This is a WIP, so the front-end hasn't been modified to emit these
flags just yet. Documentation and front-end switching to occur soon.

llvm-svn: 150507

llvm-svn: 150496

only be live in to a block if it is the function entry point or a landing pad.

llvm-svn: 150494

that are greater than the vector element type. For example BUILD_VECTOR
of type <1 x i1> with a constant i8 operand.
This patch fixes the assertion.

llvm-svn: 150477

llvm-svn: 150471

llvm-svn: 150467

llvm-svn: 150466

Move old movl vector_shuffle patterns. Not needed anymore since vector_shuffles shouldn't reach isel.

llvm-svn: 150462

Rename getExceptionAddressRegister() to getExceptionPointerRegister() for consistency with setExceptionPointerRegister(...).

llvm-svn: 150460

llvm-svn: 150457

llvm-svn: 150449

llvm-svn: 150447

llvm-svn: 150444

llvm-svn: 150441

This folds a simple loop tail into a loop latch. It covers the common (in fortran) case of postincrement loops. It's a "free" way to expose this type of loop to downstream loop optimizations that bail out on non-canonical loops (getLoopLatch is a heavily used check).

llvm-svn: 150439

llvm-svn: 150438

marking them as "live-in" into a BB ruins some invariants that the back-end
tries to maintain.

llvm-svn: 150437

llvm-svn: 150436

llvm-svn: 150433

The scheduler will sometimes check the implicit-def list on instructions
to properly handle pre-colored DAG edges.

Also check any register mask operands for physreg clobbers.

llvm-svn: 150428

llvm-svn: 150425

(but not of) a block pointer do not cause the block pointer to
escape. This fixes rdar://10803830.

llvm-svn: 150424

Clang patch (flags) will follow shortly.
The run-time library will also follow, but not immediately.

llvm-svn: 150423

v2f16 is a floating point type.  Add symbolic floating point type ranges to prevent this kind of issue in the future.

llvm-svn: 150416

llvm-svn: 150411

This is useful for clients that want to maintain compatibility
across multiple releases of LLVM. Currently users like Klee and
Mesa all have to roll their own 'parse llvm-config --version
output and generate defines' solution.

Also reuse the new macros so that version information is less
redundant/likely to fall out of sync again in the future.

llvm-svn: 150405

llvm-svn: 150404

Fix a bug in DAGCombine for the optimization of BUILD_VECTOR. We cant generate a shuffle node from two vectors of different types.

llvm-svn: 150383

llvm-svn: 150369

llvm-svn: 150365

- Use unsigned literals when the desired result is unsigned. This mostly allows unsigned/signed mismatch warnings to be less noisy even if they aren't on by default.
- Remove misplaced llvm_unreachable.
- Add static to a declaration of a function on MSVC x86 only.
- Change some instances of calling a static function through a variable to simply calling that function while removing the unused variable.

llvm-svn: 150364

Remove more vector_shuffle patterns for unpack. These should be target specific nodes when they get to isel.

llvm-svn: 150363

llvm-svn: 150362

llvm-svn: 150361

Update CanXFormVExtractWithShuffleIntoLoad to ensure bitcasts of loads only have one use. Matches DAGCombiner and prevents vector_shuffles from reaching isel.

llvm-svn: 150360

It caused 3 failures on pre-penryn and non-x86(generic) hosts.

llvm-svn: 150357

If the DEC node had more than one user, it was doing this lowering but
leaving the original DEC node around and so decrementing twice.

Fixes PR11964.

llvm-svn: 150356

This patch addresses the problem of poor code generation for the zext
v8i8 -> v8i32 on AVX machines. The codegen often scalarizes ANY_EXTEND nodes.
The DAGCombiner has two optimizations that can mitigate the problem. First,
if all of the operands of a BUILD_VECTOR node are extracted from an ZEXT/ANYEXT
nodes, then it is possible to create a new simplified BUILD_VECTOR which uses
UNDEFS/ZERO values to eliminate the scalar ZEXT/ANYEXT nodes.
Second, another dag combine optimization lowers BUILD_VECTOR into a shuffle
vector instruction.

In the case of zext v8i8->v8i32 on AVX, a value in an XMM register is to be
shuffled into a wide YMM register.

This patch modifes the second optimization and allows the creation of
shuffle vectors even when the newly generated vector and the original vector
from which we extract the values are of different types.

llvm-svn: 150340

llvm-svn: 150332

the process. Some of these are still a bit gross.

Still, this cuts 80 some lines out of this ridiculous file. ;]

llvm-svn: 150331