vector_shuffle v1, v2, <2, 6, 3, 7>

I.e.

         vector_shuffle v, undef, <2, 2, 3, 3>

MMX only has a shuffle for v4i16 vectors. It needs to use the unpackh for
this type of operation.

llvm-svn: 36403

llvm-svn: 36355

llvm-svn: 36318

X86 32 bits.

llvm-svn: 36283

llvm-svn: 36213

it is defined in.

llvm-svn: 36196

Also, fixed static case in presence of eax livin. This fixes PR331

PS: Why don't we still have push/pop instructions? :)
llvm-svn: 36195

target for tabs checking.

llvm-svn: 36146

llvm-svn: 35940

llvm-svn: 35845

llvm-svn: 35840

getRegClassForInlineAsmConstraint to being handled by
getRegForInlineAsmConstraint.  This allows us to let the llvm register allocator
allocate, which gives us better code.  For example, X86/2007-01-29-InlineAsm-ir.ll
used to compile to:

_run_init_process:
        subl $4, %esp
        movl %ebx, (%esp)
        xorl %ebx, %ebx
        movl $11, %eax
        movl %ebx, %ecx
        movl %ebx, %edx
        # InlineAsm Start
        push %ebx ; movl %ebx,%ebx ; int $0x80 ; pop %ebx
        # InlineAsm End

Now we get:
_run_init_process:
        xorl %ecx, %ecx
        movl $11, %eax
        movl %ecx, %edx
        # InlineAsm Start
        push %ebx ; movl %ecx,%ebx ; int $0x80 ; pop %ebx
        # InlineAsm End

llvm-svn: 35804

used with x constraints.

llvm-svn: 35803

llvm-svn: 35799

llvm-svn: 35521

llvm-svn: 35394

llvm-svn: 35392

comparison operators.

llvm-svn: 35385

llvm-svn: 35353

#include <mmintrin.h>

extern __m64 C;

void baz(__v2si *A, __v2si *B)
{
  *A = C;
  _mm_empty();
}

We get this:

_baz:
        call "L1$pb"
"L1$pb":
        popl %eax
        movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
        movq (%eax), %mm0
        movl 4(%esp), %eax
        movq %mm0, (%eax)
        emms
        ret

GCC gives us this:

_baz:
        pushl   %ebx
        call    L3
"L00000000001$pb":
L3:
        popl    %ebx
        subl    $8, %esp
        movl    L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
        movl    (%eax), %edx
        movl    4(%eax), %ecx
        movl    16(%esp), %eax
        movl    %edx, (%eax)
        movl    %ecx, 4(%eax)
        emms
        addl    $8, %esp
        popl    %ebx
        ret

llvm-svn: 35351

not just the first letter.  No functionality change.

llvm-svn: 35322

llvm-svn: 35319

llvm-svn: 35266

llvm-svn: 35245

llvm-svn: 35152

llvm-svn: 35129

llvm-svn: 35125

llvm-svn: 35118

llvm-svn: 35108

 a legal target address immediate or scale.

llvm-svn: 35073

llvm-svn: 35070

the addition. Please let me know if you have suggestions.

llvm-svn: 35055

moves, loads, etc. are recognized.

llvm-svn: 35031

zext/sext/aext stuff.

llvm-svn: 35008

load and stores.

llvm-svn: 35002

llvm-svn: 34978

from formal attributes' flags processing.

llvm-svn: 34963

llvm-svn: 34857

llvm-svn: 34849

passed in registers, not directly from the pregs themselves.

llvm-svn: 34838