of various 4-element vectors.

llvm-svn: 27739

one type (v4i32) so that we don't have to write patterns for each type, and
so that more CSE opportunities are exposed.

llvm-svn: 27731

Remove some done items from the todo list.

llvm-svn: 27729

llvm-svn: 27726

go away when I start using evan's binop type canonicalizer

llvm-svn: 27725

llvm-svn: 27714

separate functions, for simplicity and code clarity.

llvm-svn: 27693

functions, which makes the code much cleaner :)

llvm-svn: 27692

tested by CodeGen/Generic/vector.ll

llvm-svn: 27657

llvm-svn: 27654

llvm-svn: 27651

different types.

Codegen spltw(0x7FFFFFFF) and spltw(0x80000000) without a constant pool load,
implementing PowerPC/vec_constants.ll:test1.  This compiles:

typedef float vf __attribute__ ((vector_size (16)));
typedef int vi __attribute__ ((vector_size (16)));
void test(vi *P1, vi *P2, vf *P3) {
  *P1 &= (vi){0x80000000,0x80000000,0x80000000,0x80000000};
  *P2 &= (vi){0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF,0x7FFFFFFF};
  *P3 = vec_abs((vector float)*P3);
}

to:

_test:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        vspltisw v0, -1
        vslw v0, v0, v0
        lvx v1, 0, r3
        vand v1, v1, v0
        stvx v1, 0, r3
        lvx v1, 0, r4
        vandc v1, v1, v0
        stvx v1, 0, r4
        lvx v1, 0, r5
        vandc v0, v1, v0
        stvx v0, 0, r5
        mtspr 256, r2
        blr

instead of (with two constant pool entries):

_test:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        li r6, lo16(LCPI1_0)
        lis r7, ha16(LCPI1_0)
        li r8, lo16(LCPI1_1)
        lis r9, ha16(LCPI1_1)
        lvx v0, r7, r6
        lvx v1, 0, r3
        vand v0, v1, v0
        stvx v0, 0, r3
        lvx v0, r9, r8
        lvx v1, 0, r4
        vand v1, v1, v0
        stvx v1, 0, r4
        lvx v1, 0, r5
        vand v0, v1, v0
        stvx v0, 0, r5
        mtspr 256, r2
        blr

GCC produces (with 2 cp entries):

_test:
        mfspr r0,256
        stw r0,-4(r1)
        oris r0,r0,0xc00c
        mtspr 256,r0
        lis r2,ha16(LC0)
        lis r9,ha16(LC1)
        la r2,lo16(LC0)(r2)
        lvx v0,0,r3
        lvx v1,0,r5
        la r9,lo16(LC1)(r9)
        lwz r12,-4(r1)
        lvx v12,0,r2
        lvx v13,0,r9
        vand v0,v0,v12
        stvx v0,0,r3
        vspltisw v0,-1
        vslw v12,v0,v0
        vandc v1,v1,v12
        stvx v1,0,r5
        lvx v0,0,r4
        vand v0,v0,v13
        stvx v0,0,r4
        mtspr 256,r12
        blr

llvm-svn: 27624

Canonicalize BUILD_VECTOR's that match VSPLTI's into a single type for each
form, eliminating a bunch of Pat patterns in the .td file and allowing us to
CSE stuff more aggressively.  This implements
PowerPC/buildvec_canonicalize.ll:VSPLTI

llvm-svn: 27614

each other.  This implements CodeGen/PowerPC/vxor-canonicalize.ll

llvm-svn: 27609

llvm-svn: 27594

llvm-svn: 27593

llvm-svn: 27592

llvm-svn: 27588

doesn't say where they go :-/

llvm-svn: 27579

No functionality change.

llvm-svn: 27577

llvm-svn: 27544

llvm-svn: 27543

letting the code generator handle them directly.

llvm-svn: 27539

constant pool load.

llvm-svn: 27538

No functionality changes.

llvm-svn: 27536

entry point of a function.

llvm-svn: 27494

llvm-svn: 27491

llvm-svn: 27470

llvm-svn: 27469

Convert vsldoi(x,x) to work the same way other (x,x) cases work.

llvm-svn: 27467

llvm-svn: 27463

llvm-svn: 27457

llvm-svn: 27453

lower it and LLVM to have one fewer intrinsic.  This implements
CodeGen/PowerPC/vec_shuffle.ll

llvm-svn: 27450

vperm with a perm mask lvx'd from the constant pool.

llvm-svn: 27448

llvm-svn: 27442

llvm-svn: 27440

llvm-svn: 27439

llvm-svn: 27433

llvm-svn: 27425