Test case at Transformations/SCCP/2007-05-16-InvokeCrash.ll

llvm-svn: 37185

in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer
has a better chance of producing ldm/stm.  Ideally you would get cooperation
from the RA as well but this is not there yet.

llvm-svn: 37179

llvm-svn: 37175

Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an optimization to fold VECTOR_SHUFFLE to a zero vector.

llvm-svn: 37173

llvm-svn: 37172

i128 integers.  The 64-bit masks are not wide enough to represent the results.
These should be converted to APInt someday.

llvm-svn: 37169

add expand support for ADDC/SUBC/ADDE/SUBE so we can codegen 128-bit add/sub on 32-bit (or less) targets

llvm-svn: 37168

cause other regressions.

llvm-svn: 37160

llvm-svn: 37159

llvm-svn: 37158

of verifying result values when debugging.

llvm-svn: 37156

llvm-svn: 37154

undefined behavior when the width > 64 bits.

llvm-svn: 37153

llvm-svn: 37141

llvm-svn: 37139

llvm-svn: 37138

llvm-svn: 37134

llvm-svn: 37130

llvm-svn: 37126

llvm-svn: 37125

llvm-svn: 37124

llvm-svn: 37123

llvm-svn: 37121

llvm-svn: 37120

llvm-svn: 37119

Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal operand so they are not predicable.

llvm-svn: 37118

llvm-svn: 37117

not being generated correctly because the shl operator does not mutate its
object but returns a new value. Also, make the distinction between radix
16 and the others more clear.

llvm-svn: 37111

llvm-svn: 37105

runtime.

llvm-svn: 37104

llvm-svn: 37103

This fixes PR1423

llvm-svn: 37102

llvm-svn: 37100

llvm-svn: 37098

llvm-svn: 37097

on. This helps to speed up the debugging time by showing computational
results as the program executes.

llvm-svn: 37095

llvm-svn: 37094

llvm-svn: 37093

llvm-svn: 37092

llvm-svn: 37089