simplifying them and exposing more information to tblgen.  It would be nice
if other target authors adopted this as well, particularly arm since it has fastisel.

llvm-svn: 129676

kind of predicate: one that is specific to imm nodes.  The predicate function
specified here just checks an int64_t directly instead of messing around with
SDNode's.  The virtue of this is that it means that fastisel and other things
can reason about these predicates.

llvm-svn: 129675

structure and fix some fixmes.  We now have a TreePredicateFn class
that handles all of the decoding of these things.  This is an internal
cleanup that has no impact on the code generated by tblgen.

llvm-svn: 129670

2. implement rdar://9289501 - fast isel should fold trivial multiplies to shifts
3. teach tblgen to handle shift immediates that are different sizes than the 
   shifted operands, eliminating some code from the X86 fast isel backend.
4. Have FastISel::SelectBinaryOp use (the poorly named) FastEmit_ri_ function
   instead of FastEmit_ri to simplify code.

llvm-svn: 129666

when we have a global variable base an an index.  Instead, just give up on
folding the global variable.

Before we'd geenrate:

_test:                                  ## @test
## BB#0:
	movq	_rtx_length@GOTPCREL(%rip), %rax
	leaq	(%rax), %rax
	addq	%rdi, %rax
	movzbl	(%rax), %eax
	ret

now we generate:

_test:                                  ## @test
## BB#0:
	movq	_rtx_length@GOTPCREL(%rip), %rax
	movzbl	(%rax,%rdi), %eax
	ret

The difference is even more significant when there is a scale
involved.

This fixes rdar://9289558 - total fail with addr mode formation at -O0/x86-64

llvm-svn: 129664

less trivial things) into a dummy lea.  Before we generated:

_test:                                  ## @test
	movq	_G@GOTPCREL(%rip), %rax
	leaq	(%rax), %rax
	ret

now we produce:

_test:                                  ## @test
	movq	_G@GOTPCREL(%rip), %rax
	ret

This is part of rdar://9289558

llvm-svn: 129662

llvm-svn: 129661

llvm-svn: 129654

llvm-svn: 129640

  error in foo.o; no .eh_frame_hdr table will be created.

llvm-svn: 129635

boundary.  <rdar://problem/8933028>

llvm-svn: 129634

rdar://problem/9292717

llvm-svn: 129619

The a bit must be encoded as 0.

rdar://problem/9292625

llvm-svn: 129618

llvm-svn: 129612

a case involving EOR, so I only added a test for ORR.

llvm-svn: 129610

llvm-svn: 129608

Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.

llvm-svn: 129606

problem as all of the other instructions we fold with CMPs.

llvm-svn: 129602

llvm-svn: 129601

fixes <rdar://problem/9287901>.

llvm-svn: 129599

Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions.

llvm-svn: 129594

Increase SubtargetFeatureKV Value and Implies fields to 64 bits since some targets are getting very close to 32 subtarget features. Also teach tablegen to error when there are more than 64 features to guard against undefined behavior. rdar://9282332

llvm-svn: 129590

Change ELF systems to use CFI for producing the EH tables. This reduces the
size of the clang binary in Debug builds from 690MB to 679MB.

llvm-svn: 129571

Luis Felipe Strano Moraes!

llvm-svn: 129558

It broke several builds.

llvm-svn: 129557

forget to right shift the source by 32 first. rdar://9287902

llvm-svn: 129556

Ref: I.1 Instruction encoding diagrams and pseudocode
llvm-svn: 129552

llvm-svn: 129551

(single element or n-element structure to all lanes).

llvm-svn: 129550

llvm-svn: 129548

llvm-svn: 129531

llvm-svn: 129527

size of the clang binary in Debug builds from 690MB to 679MB.

llvm-svn: 129518

llvm-svn: 129517

improvements, that will lead to fixing PR6627.

llvm-svn: 129504

(movzx/movsx) because they give more information. Revert that part of the patch.

llvm-svn: 129498

cases, it's much nicer and more informative reading the alias.

llvm-svn: 129497

the alias".

llvm-svn: 129485

rdar://problem/9280370

llvm-svn: 129480

Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).

rdar://problem/9280470

llvm-svn: 129471