for some reason they have a very odd MCInst form where the operands overlap, but
I haven't dug in to find out why yet.

llvm-svn: 110781

llvm-svn: 110780

llvm-svn: 110778

llvm-svn: 110762

llvm-svn: 110761

make any assumptions about when the two conditions will agree on when
to permit the loop to exit. This fixes PR7845.

llvm-svn: 110758

(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.

llvm-svn: 110754

llvm-svn: 110750

llvm-svn: 110745

Apply the same approach of SSE4.1 ptest intrinsics but
create a new x86 node "testp" since AVX introduces
vtest{ps}{pd} instructions which set ZF and CF depending
on sign bit AND and ANDN of packed floating-point sources.

This is slightly different from what the "ptest" does.
Tests comming with the other 256 intrinsics tests.

llvm-svn: 110744

create constraints from comparisons other than eq/neq.

llvm-svn: 110742

patterns generated by clang for transpose of a matrix in generic vectors.  This is made
of two parts:

1) Propagating vector extracts of hi/lo half into their users
2) Recognizing an insertion of even elements followed by the odd elements as an unpack.

Testcase to come, but this shrinks the # of shuffle instructions generated on x86 from ~40 to the minimal 8.

llvm-svn: 110734

a register before checking if it was defined.

llvm-svn: 110733

operands. We don't currently have a hook to provide "the largest super class of
A where all registers' getSubReg(subidx) is valid and in B".

llvm-svn: 110730

llvm-svn: 110726

The live interval may be used for a spill slot as well, and that spill slot
could be shared by split registers. We cannot shrink it, even if we know the
current register won't need the spill slot in that range.

llvm-svn: 110721

llvm-svn: 110720

ARM testers.

llvm-svn: 110718

llvm-svn: 110717

llvm-svn: 110714

llvm-svn: 110712

llvm-svn: 110710

Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function stack frame has a var-sized object.

Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions.

llvm-svn: 110707

When splitting a live range, the new registers have fewer uses and the
permissible register class may be less constrained. Recompute the register class
constraint from the uses of new registers created for a split. This may let them
be allocated from a larger set, possibly avoiding a spill.

llvm-svn: 110703

register is", it breaks a couple test-suite tests.

llvm-svn: 110701

parentheses from argument lists.

llvm-svn: 110692

during live range splitting.

llvm-svn: 110686

This reverts commit 110575.

Target.isAbsolute() is true if SD would be null.

llvm-svn: 110683

llvm-svn: 110667

llvm-svn: 110665

llvm-svn: 110656

reserved, not available for general allocation. This eliminates all the
extra checks for Darwin.

This change also fixes the use of FP to access frame indices in leaf
functions and cleaned up some confusing code in epilogue emission.

llvm-svn: 110655

llvm-svn: 110654

llvm-svn: 110653

llvm-svn: 110652

llvm-svn: 110650

llvm-svn: 110649

llvm-svn: 110648

llvm-svn: 110645

Refactor and simplify code to avoid redundant checks.

llvm-svn: 110642